Memory Read Circuit Feedback for Bit Voltage Separation

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Solution Overview

Problem

Existing memory technologies face challenges in accurately distinguishing between bit values based on voltage signals, due to voltage levels being close to those corresponding to adjacent bit values, leading to difficulties in reading or identifying data effectively.

Innovation Solution

The proposed solution involves a memory system with a reading device that includes two reading circuits and a feedback device. This system generates a voltage signal based on the bit value of the data, optimizing the voltage distribution curve to increase the voltage level difference between bit values and their adjacent values, thereby enhancing distinguishability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a single reading circuit is used to read data from memory, then the device complexity is low, but the measurement precision of bit values deteriorates due to overlapping voltage levels

Engineering Contradiction:
Improvebit value distinction accuracyVSAvoidreading circuit structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The reading device is divided into multiple independent reading circuits (first reading circuit and second reading circuit), each responsible for reading different bit values. This segmentation allows simultaneous measurement of multiple voltage levels, improving bit value distinction accuracy while distributing the complexity across modular components.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-dimensional voltage measurement approach to a multi-dimensional measurement space by introducing multiple reading circuits that operate in parallel. This dimensional expansion enables simultaneous discrimination of multiple bit values that would otherwise overlap in a single measurement channel.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If voltage levels are used to represent bit values, then the data storage capacity is high, but the reliability of data reading deteriorates when voltage levels are close to each other

Engineering Contradiction:
Improvedata reading accuracyVSAvoidvoltage level differentiation
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent replaces the traditional single voltage-level measurement system with a multi-circuit electrical measurement system. By using multiple reading circuits with different threshold voltages, the system can reliably distinguish between close voltage levels that represent different bit values, thereby improving data reading accuracy without sacrificing storage capacity.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Measurement precision

If the voltage distribution curve is optimized to increase voltage level differences, then the measurement precision of bit values improves, but the device complexity increases due to additional reading circuits

Engineering Contradiction:
Improvevoltage level distinctionVSAvoidreading device structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Multiple reading circuits are merged into a single integrated reading device structure that shares common components such as the memory cell array and control logic. This merging approach enables improved voltage level distinction through parallel measurement while minimizing the increase in overall device complexity by reusing existing structural elements.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12217795B2Memory and operating method thereof
Publication Date: 2025.02.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12217795B2 patent drawing
  • US12217795B2 patent drawing
  • US12217795B2 patent drawing

AI summary

A memory includes a memory device, a reading device and a feedback device. The memory device stores a plurality of bits. The reading device includes first and second reading circuits coupled to the memory device. The second reading circuit is coupled to the first reading circuit at a first node. The first and second reading circuits cooperates with each other to generate a first voltage signal at the first node based on at least one first bit of the plurality of bits. The feedback device adjusts at least one of the first reading circuit or the second reading circuit based on the first voltage signal. The first and second reading circuits generate a second voltage signal, different from the first voltage signal, corresponding to the bits, after the at least one of the first reading circuit or the second reading circuit is adjusted by the feedback device.