Semiconductor Memory Device Read Voltage Control
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Solution Overview
Problem
Semiconductor memory devices face challenges in reducing the variation in threshold voltage of memory cell transistors, which affects the accuracy of read operations and data retention over time.
Innovation Solution
The semiconductor memory device employs a specific configuration of conductive layers and a control circuit that applies tailored voltages during read operations to manage the threshold voltage variation, ensuring stable channel voltages and reducing capacitance coupling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional read operations are performed without specialized voltage control, then the device structure remains simple, but the threshold voltage variation increases and read accuracy deteriorates
Solution Approach 1:
The patent segments the control mechanism by introducing multiple independently controllable conductive layers (first through fourth conductive layers) that can be applied with different voltages. This segmentation allows precise control of channel voltage in different regions and at different times, reducing threshold voltage variation without requiring fundamental changes to the memory cell structure.
Solution Approach 2:
The patent introduces conductive layers as intermediary elements between the control circuit and the memory cell transistors. These conductive layers act as mediators that distribute and regulate voltages to minimize capacitance coupling effects and threshold voltage variation, enabling accurate read operations without direct complex circuitry at each memory cell.
2Reliability
If standard voltage application is used during read operations, then the operation sequence remains simple, but data retention deteriorates due to threshold voltage variation
Solution Approach 1:
The patent applies preliminary voltage control by setting specific voltages on the conductive layers before performing the read operation. The control circuit pre-configures the voltage states of the first through fourth conductive layers to minimize threshold voltage variation before data is read, ensuring data retention is maintained throughout the operation sequence.
Solution Approach 2:
The patent employs periodic voltage application sequences where different voltage patterns are applied to the conductive layers at different stages of the read operation. This periodic control ensures that threshold voltage variation is minimized at critical moments while maintaining simple overall device structure.
3Measurement precision
If no voltage management is applied to conductive layers, then the operation remains fast, but threshold voltage variation increases and read accuracy decreases
Solution Approach 1:
The patent changes the voltage parameters applied to the conductive layers during the read operation. By dynamically adjusting the voltages on the first through fourth conductive layers, the system minimizes threshold voltage variation and capacitance coupling effects, achieving high read accuracy without significant time penalty through optimized voltage sequencing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the variation in threshold voltage, enhancing the accuracy of read operations and improving data retention by maintaining channel voltages and minimizing voltage fluctuations.
Implementation Method 1
reducing capacitance coupling effects
Data Source
AI summary
A semiconductor memory device includes a memory pillar; first and second conductive layers on either side of the memory pillar; third and fourth conductive layers and fifth and sixth conductive layer respectively below and above first and second conductive layers; seventh and eighth conductive layers below third and fourth conductive layers; ninth and tenth conductive layers above fifth and sixth conductive layers; memory cells formed between a respective first through tenth conductive layers and the memory pillar; and a control circuit, which applies a read voltage to the first conductive layer, a negative voltage to second, fourth, and sixth conductive layers, and a read pass voltage to other conductive layers, applies the read pass voltage to first, second, fourth, and sixth conductive layers, applies a ground voltage or lower to a first group of conductive layers, and then a ground voltage to a second group of conductive layers.