3D Memory Read Accuracy via Auto-Referenced Voltage Adjustment

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing memory devices, particularly 3D array memory cells, face challenges in efficient writing and reading operations due to variable electrical characteristics, leading to inaccuracies and reliability issues over time, especially with phase-change materials like PCM cells.

Innovation Solution

The proposed solution involves an auto-referenced read technique that adjusts the read reference voltage based on the statistical properties of the voltage distribution of memory cells, encoding user data to balance the number of bits in specific logic states, and a programming method that masks already set bits to reduce the need for high programming voltages, thereby improving read accuracy and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional write techniques are used in 3D array memory cells, then write operations can be performed, but read accuracy deteriorates due to variable electrical characteristics and threshold voltage distribution

Engineering Contradiction:
Improveread accuracyVSAvoidread reliability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent implements feedback by measuring the actual threshold voltage distribution of memory cells and using this information to dynamically adjust the read reference voltage. The system continuously monitors voltage distribution characteristics and modifies read operations accordingly, creating a closed-loop control system that adapts to changing memory cell conditions and maintains high read accuracy.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the read reference voltage parameter based on the measured statistical properties of threshold voltage distribution. Instead of using a fixed reference voltage, the system dynamically adjusts this critical parameter to match the actual memory cell characteristics, thereby optimizing read accuracy under varying conditions.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If high programming voltages are applied to ensure reliable writing, then write reliability improves, but memory cell stress increases leading to reduced longevity

Engineering Contradiction:
Improvewrite reliabilityVSAvoidmemory cell longevity
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent applies dynamic write voltage adjustment where the programming voltage is adapted based on the measured threshold voltage distribution and individual memory cell characteristics. Instead of uniformly applying high voltages to all cells, the system dynamically determines the appropriate voltage level for each cell or group of cells, ensuring reliable programming while minimizing unnecessary stress.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements localized write voltage adjustment where different voltage levels are applied to different regions or groups of memory cells based on their specific characteristics. This allows high voltage to be applied only where necessary to achieve reliable programming, while other cells receive lower voltages, thereby reducing overall stress and improving longevity.

Inventive Principle:
Principle #3Local quality

3Ease of operation

If traditional read reference voltage is used, then read operations are simple, but read accuracy deteriorates due to threshold voltage distribution variations

Engineering Contradiction:
Improveread operation simplicityVSAvoidread accuracy
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent uses feedback from threshold voltage distribution measurements to automatically adjust the read reference voltage. The system measures the voltage distribution characteristics and uses this information to determine the optimal reference voltage, eliminating the need for manual calibration while maintaining high read accuracy.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent implements self-adjusting read operations where the memory system automatically determines and applies the appropriate read reference voltage based on its own measured characteristics. This self-service approach maintains simplicity by eliminating external calibration requirements while achieving high accuracy through automatic adaptation.

Inventive Principle:
Principle #25Self-service

4Quantity of substance

If memory cell density is increased to improve storage capacity, then storage capacity improves, but electrical characteristics become more variable affecting read accuracy

Engineering Contradiction:
Improvestorage capacityVSAvoidread accuracy
Core Design Contradiction:
Quantity of substanceVSMeasurement precision

Solution Approach 1:

The patent adjusts the read reference voltage parameter based on the statistical properties of threshold voltage distribution that arise from high-density cell arrangements. By dynamically changing this critical parameter to match the actual voltage distribution in dense arrays, the system maintains high read accuracy despite the increased variability inherent in high-density configurations.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent modifies write voltage parameters based on measured threshold voltage distributions to program memory cells with appropriate voltage levels. This adaptive approach ensures reliable programming while accounting for the electrical characteristic variations that occur in high-density memory arrays, thereby maintaining both storage capacity and read accuracy.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240395297A1Methods and systems for improving read and write of memory cells
Publication Date: 2024.11.28 MICRON TECHNOLOGY INC
  • US20240395297A1 patent drawing
  • US20240395297A1 patent drawing
  • US20240395297A1 patent drawing

AI summary

A method for accessing of memory cells where a set of user data is stored in a plurality of memory cells of the memory array, including: latching a current row address of a selected plurality of memory access; comparing a last row address with the current row address; if the result of the comparison is negative, executing a leakage compensation algorithm through a memory sensing circuitry; if the result of the comparison is positive, waiting for the completion of a write to read procedure on the selected plurality of memory cells.