Multi-Level Memory Read Voltage Tuning for Lower Bit Flips
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Solution Overview
Problem
Non-volatile memory devices with multi-bit per memory cell storage architecture face narrower read margins, making them vulnerable to noise, program/read disturbances, coupling issues, and charge loss, leading to increased read errors.
Innovation Solution
A method is introduced to determine optimal read voltages by performing shift-read operations with offset voltages and comparing bit flip information to identify the best read voltage, reducing read errors through a combination of read retry operations and error correction codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit per memory cell storage architecture is used, then storage capacity is improved, but read margins become narrower and read errors increase
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting read voltages based on detected bit flip patterns. The system modifies read voltage parameters (increasing or decreasing by incremental steps) to optimize the separation between threshold voltage distributions of programmed and erased states, thereby improving read margins and reducing read errors in multi-bit memory cells
2Reliability
If read retry operations with voltage adjustments are performed, then read error correction is improved, but operation latency increases
Solution Approach 1:
The patent implements preliminary action by performing shift-read operations with offset voltages before the actual read operation. These preliminary operations detect bit flip patterns and determine the direction and magnitude of voltage adjustment needed, allowing the system to prepare optimal read voltages in advance and minimize latency during data retrieval
Solution Approach 2:
The system employs feedback mechanisms by monitoring bit flip information from shift-read operations and using this information to dynamically adjust read voltages. The feedback loop compares bit flip patterns against threshold criteria and automatically modifies subsequent read operations, enabling adaptive error correction that balances reliability improvement with minimal latency overhead
Data Source
AI summary
A method of operating a memory system includes performing a first read operation with a first read voltage of a first single read level, performing a first shift-read operation with the first read voltage plus a first offset voltage, performing a second shift-read operation with the first read voltage minus the first offset voltage, and in response to that a difference between first bit flip information of the first shift-read operation and second bit flip information of the second shift-read operation is equal to or lower than a threshold, determining that the first read voltage is a first optimal read voltage. The first single read level of a first page is under a multi-level architecture.