Memory Read-Level Voltage Validation Using Bit-Count Feedback
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Solution Overview
Problem
Existing memory device calibration techniques exhibit high latency and are 'blind' to voltage distribution shifts, leading to incorrect read data and increased memory access latency.
Innovation Solution
Utilize memory device-originated bit count information to validate read voltage levels by comparing actual and expected bit counts, adjusting read levels to align with correct voltage distribution valleys, thereby improving read operation efficiency and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing memory device calibration techniques are used, then read operations can be performed, but high latency and incorrect read data occur due to being blind to voltage distribution shifts
Solution Approach 1:
The patent implements feedback by using actual bit count information from memory cells to validate and adjust read level voltages. The system compares expected bit counts (based on programmed data) with actual bit counts (from read operations) and uses this feedback to correct voltage distribution shifts, thereby improving read data accuracy while maintaining low latency
Solution Approach 2:
The patent performs preliminary validation of read levels by comparing expected and actual bit counts before final data retrieval. This preliminary check allows the system to detect voltage shifts early and adjust read levels proactively, preventing incorrect reads and reducing re-calibration latency
2Reliability
If calibration operations are performed to adjust read levels, then read data accuracy improves, but memory access latency increases
Solution Approach 1:
The patent enables self-service by allowing the memory device to perform self-validation using its own bit count information. The system uses internally available data (expected vs. actual bit counts) to detect and correct voltage shifts without requiring external calibration operations, thereby maintaining accuracy while minimizing latency
Solution Approach 2:
The patent dynamically adjusts read level voltage parameters based on detected voltage distribution shifts. By changing voltage parameters in response to bit count comparisons, the system maintains read accuracy without requiring full calibration sequences, reducing the time penalty associated with traditional calibration methods
3Productivity
If read levels are not adjusted for voltage distribution shifts, then memory access remains fast, but incorrect read data is returned
Solution Approach 1:
The system uses feedback from bit count comparisons to detect voltage shifts that would otherwise go unnoticed. By continuously monitoring whether actual bit counts match expected bit counts, the system can identify when voltage distribution shifts are occurring and adjust read levels accordingly, maintaining both speed and accuracy
Solution Approach 2:
The patent replaces traditional mechanical calibration systems with an information-based validation approach. Instead of using complex calibration hardware or time-consuming calibration sequences, the system substitutes a software-based bit count comparison mechanism that validates read levels using logical operations, maintaining high access speeds while ensuring data correctness
Data Source
AI summary
Described are systems and methods for validating read level voltage in memory devices. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: causing a read level voltage to be applied to a specified wordline of the plurality of wordlines; receiving an actual bit count reflecting a number of memory cells that have their respective threshold voltages below the read level voltage; and responsive to determining that a difference of an expected bit count and the actual bit count exceeds a predetermined threshold value, adjusting the read level voltage.