Semiconductor Memory Command Scheduling for Read-Write Overlap
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently managing read operations while executing write operations, leading to delays and inefficiencies due to the need for additional commands to verify readiness states and suspend operations.
Innovation Solution
The semiconductor memory device is configured to receive a first command set and reject write or erase operations, allowing it to execute read operations based on a separate command set, enabling it to suspend write operations and initiate read operations without additional verification commands, thus optimizing command sequences and reducing processing delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory device executes write operations, then data storage is achieved, but read operations are delayed due to the need for additional verification commands and operation suspension
Solution Approach 1:
The memory device checks the busy signal in advance to determine whether a write operation is currently being executed. Based on this preliminary check, the device proactively suspends the write operation and initiates the read operation before the host would normally issue the read command, thereby reducing the overall processing delay.
Solution Approach 2:
The memory device dynamically adjusts its operation state by transitioning between executing write operations, suspending write operations, and executing read operations based on the host's command timing and the busy signal status. This dynamic state adjustment allows the device to optimize the timing of read operations without compromising data integrity.
2Reliability
If the memory device uses additional commands to verify readiness states, then operation safety is ensured, but command sequence complexity increases
Solution Approach 1:
The memory device autonomously monitors its own busy signal state and makes decisions about suspending write operations and initiating read operations without requiring additional verification commands from the host. This self-service approach ensures operation safety while simplifying the command sequence by eliminating redundant host-side verification steps.
Solution Approach 2:
The memory device uses the busy signal as feedback to determine the current operation state. Based on this feedback, the device automatically adjusts its behavior by suspending write operations when appropriate and initiating read operations, thereby ensuring operational reliability without increasing command sequence complexity.
3Productivity
If the memory device waits for write operation completion before executing read operations, then data integrity is maintained, but system efficiency decreases
Solution Approach 1:
The memory device performs preliminary checks of the busy signal to determine whether a write operation is in progress. When the check indicates a write operation is active, the device proactively suspends the write operation and initiates the read operation in advance, eliminating the need for the host to wait for write completion before issuing read commands.
Solution Approach 2:
By suspending write operations and initiating read operations overlapping in time, the memory device ensures that useful actions (read operations) continue without interruption rather than waiting for write operations to complete. This continuity approach maintains data integrity while significantly improving system efficiency and reducing waiting time.
Data Source
AI summary
A semiconductor memory device includes a memory cell array and a control circuit configured to receive a first command set, reject a second command set related to a write operation or an erase operation, in a first time period of executing a first operation on the memory cell array in response to the first command set, receive a third command set related to a read operation in the first time period, and execute the read operation on the memory cell array in response to the third command set.