Memory Read-Back ECC Monitoring for dDRDF Fault Detection
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Solution Overview
Problem
Standard memory testing methods, such as ECC and MBIST, are insufficient to detect dynamic Deceptive Read Destructive Faults (dDRDF) in FinFET RAMs, which can lead to unexpected failures during operation, especially in critical systems, as these faults may only appear after aging and are not adequately addressed by existing error correction and self-testing methods.
Innovation Solution
A method and system that involves an error detection module generating sequential read requests to a memory module, receiving error correction codes, and providing an alert if errors are detected, allowing for early warning of increasing failure rates without disrupting normal operation, specifically designed for FinFET RAMs with feature sizes of 28nm or smaller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard ECC and MBIST methods are used for memory testing, then basic error correction and self-testing are provided, but dynamic Deceptive Read Destructive Faults (dDRDF) cannot be detected, leading to unexpected failures during operation
Solution Approach 1:
The error detection module is nested within the existing memory system architecture, integrating with the memory controller and ECC logic. The module embeds itself in the data path between the processor and memory module, allowing it to intercept and analyze memory transactions without requiring a separate external testing system. This nested integration enables advanced dDRDF detection while maintaining compatibility with existing ECC and MBIST infrastructure.
Solution Approach 2:
The error detection module performs preliminary analysis of memory read operations by examining ECC codes and data patterns before errors manifest as failures. It proactively monitors for signs of dDRDF during normal memory operations and can trigger early warnings or corrective actions before the fault becomes critical, rather than waiting for failure to occur.
2Reliability
If memory testing is performed continuously to detect dDRDF early, then reliability improves, but normal memory operations may be disrupted or slowed
Solution Approach 1:
The error detection module applies partial monitoring to memory operations, focusing ECC code analysis and error pattern detection only on critical or suspicious memory accesses rather than uniformly analyzing every single operation. It selectively intensifies monitoring based on detected error patterns, applying more rigorous checking only when dDRDF symptoms are suspected, thereby balancing detection effectiveness with operational performance.
Solution Approach 2:
The module implements periodic deep analysis of memory operations at intervals rather than continuous monitoring. It can perform comprehensive error pattern analysis at scheduled intervals or after a threshold number of operations, while maintaining lighter-weight real-time monitoring in between. This periodic approach enables thorough dDRDF detection without continuously impacting memory operation throughput.
3Reliability
If standard testing methods are used, then the system operates transparently without additional components, but insufficient early warning is provided for increasing failure rates
Solution Approach 1:
The error detection module acts as an intermediary component between the processor and memory module, intercepting memory transactions and analyzing ECC codes without requiring fundamental changes to existing memory architecture. It mediates between standard memory operations and advanced error detection requirements, providing dDRDF detection capabilities while maintaining compatibility with existing ECC and memory control infrastructure.
Data Source
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AI summary
The disclosure relates to a method and system for memory testing to detect memory errors during operation of a memory module. Example embodiments include a method of detecting an error in a memory module (101), the method comprising the sequential steps of: i) receiving (302) a request from a processor executing an application for a read or write operation at a location of the memory module (101) identified by an address; ii) outputting data (304) from, or writing to, the location of the memory module (101); iii) generating(306) by an error detection module (102) a further read request for the location of the memory module (101) identified by the address; iv) receiving (307) at the error detection module (102) an error correction code from the memory module (101) for the location identified by the address; and vi) providing (311) by the error detection module (102) an alert output for the address if the error correction code indicates an error.