Memory Readback ECC Monitoring for dDRDF Fault Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Standard memory testing methods, such as ECC and MBIST, are insufficient to detect dynamic Deceptive Read Destructive Faults (dDRDF) in FinFET RAMs, which can lead to unexpected failures during operation, especially in critical systems, as these faults may only appear after aging and are not adequately addressed by existing error correction and self-testing methods.
Innovation Solution
A method and system that involves an error detection module generating repeated read requests for a memory module address to detect errors through error correction codes, allowing for early warning of impending memory failures without disrupting normal operation, utilizing multiplexers to control read requests and provide alerts when errors are detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard ECC and MBIST methods are used for memory testing, then basic error detection is provided, but dynamic Deceptive Read Destructive Faults (dDRDF) in FinFET RAMs cannot be detected
Solution Approach 1:
The patent applies preliminary action by performing repeated read requests to a memory location before normal operation to activate and detect dDRDF faults. The error detection module proactively conducts N consecutive read requests (where N≥2) to a target address, allowing faults that manifest after multiple reads to be detected before they affect system operation. This preliminary testing approach enables early detection of aging-related faults in FinFET RAM without waiting for actual system failures.
2Reliability
If repeated read requests are performed to detect dDRDF, then fault detection capability is improved, but memory access time increases
Solution Approach 1:
The patent implements periodic action by conducting repeated read requests at regular intervals determined by parameter N. The error detection module periodically performs N consecutive reads to monitor memory health, balancing detection capability with performance. This periodic monitoring approach allows the system to detect faults that develop over time while maintaining predictable memory access patterns and avoiding continuous interference with normal operation.
Solution Approach 2:
The patent applies partial action by performing a limited number N of repeated read requests rather than continuous monitoring. This partial testing approach provides sufficient detection capability for dDRDF faults while minimizing the time overhead. The parameter N can be optimized to achieve an acceptable balance between detection sensitivity and performance impact, conducting just enough repeated reads to detect faults without excessive time loss.
3Reliability
If memory testing is performed during operation, then early warning of failures is provided, but normal memory operation may be disrupted
Solution Approach 1:
The patent applies segmentation by separating the error detection function from normal memory operation. The error detection module operates independently, conducting repeated read requests to specific target addresses while the rest of the memory system continues normal operations. This segmentation allows failure warning to be generated without disrupting overall system functionality, as the testing is confined to specific memory locations and time intervals.
Solution Approach 2:
The patent uses an intermediary approach by introducing an error detection module that acts as a mediator between the memory system and the processor. This module intercepts memory access requests, performs repeated reads for detection purposes, and then allows normal operation to proceed. The intermediary structure enables monitoring without direct interference with the main memory operation flow, providing early warnings while maintaining system usability.
Data Source
AI summary
The disclosure relates to a method and system for memory testing to detect memory errors during operation of a memory module. Example embodiments include a method of detecting an error in a memory module (101), the method comprising the sequential steps of: i) receiving (302) a request from a processor executing an application for a read or write operation at a location of the memory module (101) identified by an address; ii) outputting data (304) from, or writing to, the location of the memory module (101); iii) generating (306) by an error detection module (102) a further read request for the location of the memory module (101) identified by the address; iv) receiving (307) at the error detection module (102) an error correction code from the memory module (101) for the location identified by the address; and vi) providing (311) by the error detection module (102) an alert output for the address if the error correction code indicates an error.