Non-Volatile Memory Reading Circuit Without Reference Element
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing solutions for reading data from non-volatile memory devices are not compatible with the requirements of size reduction and increased electrical performance, particularly in terms of reading speed and reduced access time and consumption, as dictated by technological advancements.
Innovation Solution
A reading circuit that eliminates the need for a reference circuit element by utilizing a hierarchical column decoding system with local and global decoding levels, where the comparison between bitlines allows for charge division between parasitic capacitances associated with local and global bitlines to determine the stored data, generating a digital output signal without requiring a reference current or memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a reference circuit element is used for reading memory cells, then measurement precision is improved, but device complexity and area occupation increase
Solution Approach 1:
The patent removes the reference circuit element from the memory reading system entirely. Instead of using a separate reference cell or current generator, the invention uses the bitline itself as the reference by comparing the selected bitline voltage against an unselected bitline voltage, thereby eliminating the need for dedicated reference circuitry while maintaining reading functionality.
Solution Approach 2:
The bitline serves multiple functions: it acts as both the signal carrying path for memory cell data and simultaneously as the reference for comparison. The unselected bitline, which would traditionally be idle or require separate reference circuitry, is repurposed as a voltage reference, making the system more efficient and reducing overall circuit complexity.
2Measurement precision
If a reference circuit element is used for reading memory cells, then measurement precision is improved, but area occupation increases
Solution Approach 1:
The reference circuit element is extracted and removed from the system. The comparison function is achieved using existing bitline structures, eliminating the need for additional reference cells, current generators, or associated circuitry that would occupy valuable chip area.
Solution Approach 2:
The reference function is merged with the existing bitline structure. Rather than having separate reference and signal paths, the invention combines these functions by using the bitline voltage itself as the reference, thereby eliminating redundant circuitry and reducing device area.
3Reliability
If conventional reading circuit is used, then reading operation is reliable, but reading speed and access time are reduced
Solution Approach 1:
The bitline is pre-charged to a reference voltage level before the actual reading operation begins. This preliminary charging action ensures that when the memory cell is accessed, the voltage comparison can occur immediately without waiting for reference circuitry to establish its state, thereby accelerating the reading process while maintaining reliability.
4Reliability
If conventional reading circuit is used, then reading operation is reliable, but electrical consumption increases
Solution Approach 1:
The reference current generator and associated power supply circuitry are removed from the system. By using the bitline voltage directly as the reference without requiring active reference current generation, the invention significantly reduces electrical consumption while maintaining reading reliability through voltage comparison.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a non-volatile memory device with improved electrical performance, reduced area occupation, and increased reading speed, allowing for efficient data reading with lower electrical consumption and smaller dimensions, without the need for reference elements.
Implementation Method 1
the comparison between bitlines allows for charge division between parasitic capacitances associated with local and global bitlines to determine the stored data
Data Source
Figure 1~2
Figure 3~4
Figure 5~6A
AI summary
A circuit (20) for reading a memory cell (3) of a nonvolatile memory device (1) provided with a memory array (2) with cells arranged in wordlines and bitlines, among which a first bitline (BL), associated to the memory cell, and a second bitline (BL'), has: a first circuit branch (22) associated to the first bitline and a second circuit branch (22') associated to the second bitline, each with a local node (N1, N1'), coupled to which is a first dividing capacitor (30), and a global node (Ng, Ng'), coupled to which is a second dividing capacitor (32); a decoder stage (23, 25) for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage (36), which has inputs that are coupleable to the global node of the first circuit branch or second circuit branch, and supplies an output signal (Sout) indicative of the datum stored; a coupling stage (40, 41), for coupling the global nodes of the first and second circuit branches; and a control unit (21) for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal.