Semiconductor Memory Reading Circuit Synchronization
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Solution Overview
Problem
The challenge is to optimize the duration of the reading operation in memory devices across varying operating temperatures, supply voltages, and manufacturing process parameters, particularly in the context of voltage ramp reading techniques, where the dead time between pre-charge and evaluation phases increases access time and affects precision.
Innovation Solution
A circuit for reading memory cells that includes a pre-charge circuit to set bit lines to a predefined voltage, a biasing circuit for applying a bias to memory and reference cells, and an evaluation circuit to determine the information content based on electric quantities, with the enabling signal provided once bit lines reach the predefined voltage, ensuring synchronized pre-charge and evaluation phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed duration pre-charge phase is used to ensure bit line charging completion, then reading precision is maintained, but access time increases due to dead time between pre-charge and evaluation phases
Solution Approach 1:
The patent implements feedback by monitoring the actual voltage level of bit lines during the pre-charge phase and using this information to generate an enabling signal. The pre-charge circuit continuously checks whether bit lines have reached the predefined voltage threshold and provides feedback to control the transition to the evaluation phase, eliminating fixed-duration dead time while ensuring charging completion.
Solution Approach 2:
The patent transitions from a static fixed-duration pre-charge phase to a dynamic pre-charge phase that adapts to actual charging conditions. The enabling signal is generated dynamically based on real-time voltage monitoring, allowing the evaluation phase to start as soon as bit lines are fully charged, thereby optimizing access time across varying operating conditions.
2Measurement precision
If pre-charge phase duration is extended to ensure bit line charging completion under all conditions, then reading accuracy is improved, but productivity decreases due to increased access time
Solution Approach 1:
The pre-charge circuit monitors bit line voltage in real-time and provides feedback to determine when charging is complete. This feedback mechanism ensures reading accuracy is maintained under all operating conditions (temperature, voltage, process variations) while automatically optimizing the pre-charge duration to minimize dead time and maximize access speed.
Solution Approach 2:
The patent changes the parameter of pre-charge duration from a fixed value to a variable parameter that adapts to actual charging conditions. By monitoring voltage levels and adjusting the pre-charge phase duration dynamically, the system achieves both high reading accuracy and fast access speed across different operating scenarios.
3Device complexity
If a fixed pre-charge duration is used, then circuit complexity is reduced, but manufacturing precision is affected due to variations in temperature, voltage, and process parameters
Solution Approach 1:
The patent introduces feedback through voltage monitoring circuits that continuously check bit line charging status. This feedback mechanism compensates for variations in temperature, supply voltage, and manufacturing process parameters, ensuring consistent and precise charging completion detection across different manufacturing batches and operating conditions.
Solution Approach 2:
The pre-charge circuit performs self-testing by monitoring its own output voltage to determine charging completion. This self-service approach eliminates the need for external timing control and automatically adapts to process variations, maintaining manufacturing precision without significantly increasing overall circuit complexity.
Data Source
AI summary
A reading circuit for reading semiconductor memory cells, adapted to be coupled to at least one memory cell and to at least one reference cell through a respective bit line, the reading circuit including: a pre-charge circuit for pre-charging the bit lines to a predefined voltage during a pre-charge phase of a reading operation on the memory cell; a biasing circuit for applying a bias to a respective control terminal of the memory cell and of the reference cell in response to an enabling signal; and for each bit line, an evaluation circuit for evaluating an electric quantity developing on the bit line as a consequence of the bias during an evaluation phase of the reading operation on the memory cell, an information content of the memory cell being determined on the basis of the electric quantity that develops on the bit lines. The enabling signal is provided by the pre-charge circuit in response to an indication that the bit lines have reached the predefined voltage.