Compressed Memory Readout Timing Compensation for Data Merge Reliability

Solution Overview

Problem

Data merge failures occur during compression read operations in memory devices due to the limited number of data lines, which are shared among multiple memory areas, leading to synchronization issues and delays.

Innovation Solution

A memory device with a plurality of memory banks, compressing circuits, merge circuits, a delay detecting circuit, and a compensating circuit to calibrate output control signals, ensuring synchronized data merging and output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If multiple memory banks share a fixed number of data lines, then the device complexity is reduced, but data merge failures occur due to synchronization issues

Engineering Contradiction:

Improvedata line configurationVSAvoiddata merging accuracy

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent applies preliminary action by detecting delays in output control signals from memory banks before the data merging process begins. The delay detection circuit measures timing differences in advance, and the compensation circuit pre-adjusts these delays so that when data merging occurs, all memory banks are already synchronized to the same timing reference, preventing merge failures

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using the delay detection circuit to continuously monitor the timing of output control signals from each memory bank. The detected delay information is fed back to the compensation circuit, which automatically adjusts the timing of individual memory banks to eliminate synchronization errors, creating a closed-loop control system that maintains reliable data merging

Inventive Principle:

Principle #23Feedback

2Productivity

If compression read operation is performed to increase output speed, then productivity is improved, but data merge failures occur due to timing synchronization issues

Engineering Contradiction:

Improvedata output speedVSAvoiddata merging accuracy

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by detecting delays in output control signals from memory banks before the data merging process begins. The delay detection circuit measures timing differences in advance, and the compensation circuit pre-adjusts these delays so that when data merging occurs, all memory banks are already synchronized to the same timing reference, preventing merge failures

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using the delay detection circuit to continuously monitor the timing of output control signals from each memory bank. The detected delay information is fed back to the compensation circuit, which automatically adjusts the timing of individual memory banks to eliminate synchronization errors, creating a closed-loop control system that maintains reliable data merging

Inventive Principle:

Principle #23Feedback

3Ease of operation

If multiple memory areas use data lines simultaneously, then ease of operation is improved, but data loss or corruption occurs due to synchronization delays

Engineering Contradiction:

Improvememory bank accessibilityVSAvoiddata integrity

Core Design Contradiction:

Ease of operationVSLoss of information

Solution Approach 1:

The patent applies preliminary action by detecting delays in output control signals from memory banks before the data merging process begins. The delay detection circuit measures timing differences in advance, and the compensation circuit pre-adjusts these delays so that when data merging occurs, all memory banks are already synchronized to the same timing reference, preventing merge failures

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using the delay detection circuit to continuously monitor the timing of output control signals from each memory bank. The detected delay information is fed back to the compensation circuit, which automatically adjusts the timing of individual memory banks to eliminate synchronization errors, creating a closed-loop control system that maintains reliable data merging

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS12512163B2Memory device and operating method of memory device

Publication Date: 2025.12.30 SK HYNIX INC

AI summary

A memory device may include memory banks comprised of memory blocks; data compressing circuits connected to memory blocks and first merge circuits. A second merge circuit receives output from the first merge circuits. A delay detecting circuit generates delay control signals by comparing the output control signals. A compensating circuit calibrates the output control signals, based on the delay control signal. An output buffer circuit latches the second merged data and outputs the second merged data, based on at least a portion of the output control signals.