Semiconductor Memory System Ready Busy Signal Control
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Solution Overview
Problem
Current NAND flash memory systems face challenges in achieving high-speed data transmission during read operations due to the sequential nature of ready/busy signal transitions, which can delay data output to the controller.
Innovation Solution
The implementation of a semiconductor memory system that includes a count circuit to control the ready/busy signal transition from a busy state to a ready state earlier in the data transmission process, allowing parallel command and data transmission before data transfer between latch circuits is complete.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the ready/busy signal transitions to ready state only after data transfer between latch circuits is complete, then data transmission accuracy is ensured, but data transmission speed deteriorates
Solution Approach 1:
The ready/busy signal transitions to the ready state in advance, before the data transfer between latch circuits is actually complete. This preliminary transition allows the controller to prepare and issue the next read command earlier, overlapping command preparation with data transfer operations, thereby reducing overall data transmission time without compromising data integrity.
2Productivity
If sequential command execution is used, then system simplicity is maintained, but productivity deteriorates
Solution Approach 1:
By transitioning the ready/busy signal to ready state beforehand, the controller can issue subsequent read commands during the data transfer period rather than waiting for completion. This creates an overlapping execution model where command preparation and data transfer occur concurrently, improving throughput without requiring complex parallel processing architectures.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, an input/output circuit configured to output read data from the semiconductor memory device, a first data latch configured to latch data read from the memory cell array as the read data, a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit, a signaling circuit configured to output a ready signal or a busy signal, and a control circuit configured to control the signaling circuit to output the busy signal while the read data is being latched in the first data latch during a read operation performed on the memory cell array and to output the ready signal while the read data latched in the first data latch is being transferred from the first latch to the second latch.