Memory Receivers with Feedback Reset for High-Speed Timing Margins
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Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining timing margins as communication speeds increase, particularly in receivers, which affect the performance of semiconductor memory devices.
Innovation Solution
Incorporating a receiver design with a buffer, decision feedback equalizer, deserializer, and reset control circuit that adaptively resets the feedback signal based on write operation status to maintain timing margins during varying communication speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If communication speed is increased to improve performance, then productivity is improved, but timing margin is reduced
Solution Approach 1:
The feedback signal reset mechanism dynamically adapts to different operation modes (write operation vs. non-write operation) by selectively resetting the feedback signal in the decision feedback equalizer only during non-write operations, allowing the system to optimize timing margins adaptively based on operational context while maintaining high communication speeds
2Productivity
If communication speed is increased to improve performance, then productivity is improved, but reliability is reduced
Solution Approach 1:
The decision feedback equalizer uses feedback signals from previous data decisions to compensate for intersymbol interference and equalize the received signal, improving reliability at high communication speeds by continuously adapting the equalization based on feedback from the received signal quality
Solution Approach 2:
The system dynamically controls the feedback signal reset based on operation mode detection, maintaining receiver stability by preventing feedback signal invalidation during write operations while enabling normal feedback operation during non-write operations, thereby ensuring reliable reception across varying operational conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed receiver design stabilizes the decision feedback equalizer and ensures the deserializer maintains timing margins by adaptively resetting the feedback signal, enhancing the operating stability and performance of semiconductor memory devices.
Implementation Method 1
a buffer configured to generate an internal data signal by comparing a received data signal with a reference voltage
Implementation Method 2
a decision feedback equalizer configured to generate a sampled signal based on a present value of the internal data signal and on a feedback signal
Implementation Method 3
a deserializer configured to generate an output data by deserializing the sampled signal
Data Source
AI summary
A receiver includes a buffer configured to generate an internal data signal by comparing a received data signal with a reference voltage, a decision feedback equalizer configured to generate a sampled signal based on a present value of the internal data signal and on a feedback signal, and configured to provide one of the sampled signal or a first logic level as the feedback signal based on a reset control signal, the sampled signal corresponding to a previous value of the internal data signal, a deserializer configured to generate an output data by deserializing the sampled signal, and a reset control circuit configured to generate the reset control signal based on operating information associated with a write operation of the data signal and configured to provide the reset control signal to the decision feedback equalizer.