Memory Receiver Circuit for Floating Output Node Prevention
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Solution Overview
Problem
In semiconductor memory apparatus receivers, signal transitions at higher frequencies lead to output nodes becoming floating, causing output signals to become irrelevant to input signals, as all transistors turn OFF during level transitions, resulting in distorted or noisy outputs.
Innovation Solution
A receiver configuration with specific transistors and voltage control units that manage output node voltages based on input signal levels and their inversions, ensuring continuous and accurate output signal generation during signal transitions, including a first input transistor for high levels, a second for low levels, and corresponding voltage control units to maintain output node voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the receiver uses a single gate of NMOS or PMOS transistor to receive the input signal, then the device complexity is reduced, but the output signal becomes irrelevant during input signal transitions due to floating output node
Solution Approach 1:
The receiver is divided into multiple parallel paths: one path handles the input signal directly through NMOS/PMOS gates, while another path handles the inverted signal. Each path has dedicated transistors (first input transistor for high level, second input transistor for low level) that operate independently, ensuring that at least one path remains active during transitions, thus preventing the floating output node problem while maintaining manageable complexity.
2Productivity
If the input signal frequency is increased to improve productivity, then the signal transmission speed is improved, but the output node becomes more prone to floating state during transitions
Solution Approach 1:
The receiver proactively prepares for signal transitions by maintaining multiple active input paths before transitions occur. The dual-path configuration with inverted and non-inverted signal processing ensures that transition periods are pre-covered by overlapping active states, allowing the system to handle higher frequencies without entering floating states, thus maintaining output node stability at high speeds.
Data Source
AI summary
A receiver of a semiconductor memory apparatus includes a first input transistor configured to be turned ON when an input signal is equal to or more than a predetermined level; a second input transistor configured to be turned ON when the input signal is equal to or less than the predetermined level; a first output node voltage control unit configured to increase a voltage level of an output node when the first input transistor is turned ON; a second output node voltage control unit configured to decrease the voltage level of the output node when the second input transistor is turned ON; a third input transistor configured to increase the voltage level of the output node when an inversion signal of the input signal is equal to or less than the predetermined voltage level; and a fourth input transistor configured to decrease the voltage level of the output node when the inversion signal of the input signal is equal to or more than the predetermined voltage level.