Memory Data Receiver Buffering for Ringback Noise Reduction
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Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining signal integrity due to ringback noise during data reception, as existing methods to reduce noise often degrade other performance characteristics such as setup time, hold time, and slew rate.
Innovation Solution
A data receiver is designed with a first buffer circuit that varies the resistance of the data path and reference voltage path based on control signals, adjusting the voltage levels of input data signals and reference voltages to generate internal signals and internal reference voltages, and a second buffer circuit compares these internal signals to reduce ringback noise without degrading signal reception characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional data reception methods are used, then device simplicity is maintained, but signal integrity deteriorates due to ringback noise
Solution Approach 1:
The buffer circuit dynamically adjusts the resistance of the data path and reference voltage path based on control signals. The first buffer circuit varies resistance to adjust voltage levels of input data signal and reference voltage, while the second buffer circuit compares the adjusted signals. This dynamic resistance adjustment reduces ringback noise and improves signal integrity without requiring a completely complex receiver architecture.
Solution Approach 2:
The invention changes the resistance parameter of the data path and reference voltage path to optimize signal reception. By varying the resistance values in response to control signals, the buffer circuit adjusts voltage levels to minimize ringback noise effects while maintaining proper signal comparison functionality.
2Reliability
If resistance adjustment is applied to reduce ringback noise, then signal integrity is improved, but control signal requirements increase
Solution Approach 1:
The control signals serve multiple functions: they control the resistance adjustment in the data path, control the resistance adjustment in the reference voltage path, and coordinate the operation of both buffer circuits. This multi-functionality reduces the need for separate control mechanisms for each adjustment, managing complexity through integrated control.
3Reliability
If voltage level adjustment is performed, then ringback noise is reduced, but power consumption increases
Solution Approach 1:
The buffer circuit adjusts voltage levels only to the extent necessary to reduce ringback noise effects. The resistance adjustment is controlled to provide just enough voltage level modification to improve signal integrity, avoiding excessive power consumption that would result from over-adjustment or continuous maximum adjustment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces ringback noise while maintaining or improving the characteristics of signal reception, resulting in enhanced signal integrity for semiconductor memory devices.
Implementation Method 1
The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage
Implementation Method 2
The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal
Data Source
AI summary
A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path. The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal.