Memory Device Receiver Self-Adjustment via Internal Control Circuit

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Solution Overview

Problem

Memory devices face inefficiencies in adjusting input/output characteristics among receivers during the test process, which can be time-consuming and affect performance, especially when multiple devices in a package need to be synchronized without host intervention.

Innovation Solution

A memory device is designed to autonomously adjust its receivers using a test signal and control circuit, allowing for simultaneous optimization of input/output characteristics without relying on a host, thereby improving operating performance and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If receivers are adjusted during the test process with host intervention, then input/output characteristics can be optimized, but the process becomes time-consuming and reduces productivity

Engineering Contradiction:
Improveinput/output characteristics optimizationVSAvoidtest process efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The memory device autonomously adjusts its own receivers using an internal control circuit that generates test signals and modifies receiver parameters without requiring host device intervention. The control circuit directly controls the receivers and uses internal memory cells as test objects, enabling self-adjustment during the test process.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system performs receiver adjustment during the test process before normal operation begins. The control circuit generates test signals and adjusts receiver parameters in advance, ensuring optimal input/output characteristics are established before the memory device enters production mode.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If multiple memory devices in a package are adjusted simultaneously without host intervention, then productivity improves, but coordination and synchronization become more complex

Engineering Contradiction:
Improveproduction speedVSAvoidcoordination complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Each memory device in the package independently performs self-adjustment of its receivers using its own control circuit. Multiple devices operate autonomously during the test process, eliminating the need for complex host-mediated coordination while maintaining synchronization through simultaneous autonomous operation.

Inventive Principle:
Principle #25Self-service

3Productivity

If the memory device autonomously adjusts receivers using internal test signals, then host intervention is eliminated and productivity increases, but the device requires additional control circuitry

Engineering Contradiction:
Improvetest process efficiencyVSAvoidcircuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The control circuit serves multiple functions: it generates test signals, controls the receivers during adjustment, selects memory cells for testing, and adjusts receiver parameters. This multi-functional approach consolidates what could be separate circuits into a single integrated control unit, minimizing the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the test signal generation, receiver control, and receiver adjustment functions into a single control circuit. Additionally, memory cells are used for both data storage and as test objects during receiver adjustment, merging two functional uses into one physical resource.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10573401B2Memory devices and memory packages
Publication Date: 2020.02.25 SAMSUNG ELECTRONICS CO LTD
  • US10573401B2 patent drawing
  • US10573401B2 patent drawing
  • US10573401B2 patent drawing

AI summary

A memory device includes a plurality of receivers that each include a first input terminal coupled to one pin of a plurality of input/output pins. The memory devices further includes a transmitter having an output terminal coupled to the first input terminals of the plurality of receivers. The memory device further includes a control circuit configured to control the transmitter to output a particular test signal. The plurality of receivers are each configured to generate output data based on receiving the particular test signal from the transmitter. The control circuit is further configured to adjust the plurality of receivers based on the output data generated by the plurality of receivers and received at the control circuit from the plurality of receivers.