Memory Device Receiver Control for Lower Standby Current
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Solution Overview
Problem
Existing memory devices, particularly NAND flash memories, face inefficiencies in current management and data transfer operations, leading to unnecessary power consumption and operational inefficiencies due to electrical coupling between memory units during write and read operations.
Innovation Solution
The implementation of a memory system with a control circuit that manages the electrical coupling between memory units by using command and address signals to control the active and standby states of receivers, optimizing data transfer and reducing unnecessary current flow during write and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrical coupling is maintained between all memory units during operations, then data transfer reliability is improved, but power consumption increases due to current flow in non-selected units
Solution Approach 1:
The memory system is divided into multiple independently controllable memory units (e.g., memory chips or dies), each with its own receiver that can be selectively activated. The control circuit applies individual chip enable signals to each memory unit, allowing only the selected memory unit to remain electrically coupled and active during data transfer operations, while non-selected units are deactivated to eliminate unnecessary current flow and reduce power consumption.
2Speed
If all receivers remain active during operations, then data transfer speed is improved, but current consumption increases unnecessarily
Solution Approach 1:
The receivers in each memory unit are designed with dynamic control capability, allowing their active state to be adjusted based on selection status. When a memory unit is selected for data transfer operations, its receiver is activated to enable high-speed data reception. When not selected, the receiver is placed in a standby or low-power state, dynamically adapting its operational status to match the actual data transfer requirements and eliminating unnecessary current consumption.
3Reliability
If electrical coupling is maintained for all memory units, then operational reliability is improved, but operational efficiency decreases due to unnecessary current flow
Solution Approach 1:
Electrical coupling and active operation are applied locally only to the selected memory unit that requires data transfer operations, rather than maintaining uniform electrical coupling across all memory units. The control circuit enables the receiver of the selected memory unit while keeping non-selected units in a high-impedance or deactivated state, ensuring that electrical coupling and current flow are confined to only the local area where they are actually needed for operational reliability.
Data Source
AI summary
A memory system includes a memory device and a memory controller. The memory device includes first to fourth pads to which respective first to fourth signals are sent from the memory controller, a memory cell array configured to store data, and a data input and output interface. The data input and output interface is configured to receive the first signal input to the first pad as a command based on a timing of a first rising edge of the fourth signal at the fourth pad after a rising edge of the second signal at the second pad, and to receive the first signal input to the first pad as an address in response to a second rising edge of the fourth signal at the fourth pad after a rising edge of the third signal at the third pad.