Memory Receiver Trip-Point Tuning for Wider Data Windows
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Solution Overview
Problem
Conventional memory testing methods face challenges in maintaining a large data recognition window due to signal quality deterioration at high speeds, necessitating the use of Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) equalizers, which are inefficient in enlarging the maximum window for data signal recognition.
Innovation Solution
A receiver design incorporating a signal receiving module with specific transistor ratios and an adjusting module using a third MOS transistor to fine-tune the voltage values, allowing for precise adjustment of the data recognition window through an operational amplifier and resistor network, enabling the enlargement of the data recognition window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high speed data transmission is used, then transmission speed is improved, but data signal quality deteriorates causing the maximum recognition window to shrink
Solution Approach 1:
The patent adjusts the trip point voltage parameter of the data receiver dynamically. By modifying the reference voltage level at which the receiver decides between logic high and logic low, the system can compensate for signal quality deterioration at high speeds and maintain accurate data recognition within an enlarged voltage window.
Solution Approach 2:
The patent introduces dynamic adjustability to the receiver's trip point through an adjusting module that can modify the reference voltage based on signal conditions. This dynamic parameter adjustment allows the system to adapt to varying signal qualities at different transmission speeds, maintaining reliability across different operating conditions.
2Reliability
If CTLE and DFE equalizers are used to enlarge the maximum recognition window, then data signal recognition is improved, but device complexity increases
Solution Approach 1:
The patent extracts the essential function of equalization and simplifies it to a trip point adjustment mechanism. Instead of implementing complex CTLE and DFE equalizer circuits, the invention focuses on adjusting the decision threshold voltage, which achieves similar signal recognition improvement with significantly reduced circuit complexity.
Solution Approach 2:
The patent replaces expensive and complex equalizer circuits with a simpler, more cost-effective trip point adjustor. The adjusting module uses basic voltage reference circuits rather than complex equalization hardware, achieving acceptable performance with lower complexity and cost.
3Reliability
If the trip point of the data receiver is adjusted to enlarge the recognition window, then data signal recognition is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent adjusts the trip point voltage to an optimal level that provides sufficient margin for signal recognition without requiring extremely precise adjustment. By setting the trip point with appropriate excess margin, the system achieves reliable recognition while tolerating normal manufacturing variations.
Solution Approach 2:
The patent designs the trip point adjustment to create a cushion or margin in the recognition window. By establishing a trip point that provides sufficient voltage margin before signal deterioration becomes critical, the system compensates for potential manufacturing variations and maintains reliable operation.
Data Source
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AI summary
Embodiments of the disclosure provide a receiver, a memory, and a testing method. The receiver includes: a signal receiving module, including a first MOS transistor and a second MOS transistor, where a gate of the first MOS transistor is configured to receive a reference signal and a gate of the second MOS transistor is configured to receive a data signal, and the signal receiving module is configured to output a comparison signal, the comparison signal being configured to represent a magnitude relationship between a voltage value of the reference signal and a voltage value of the data signal; and an adjusting module, including a third MOS transistor, where a source of the third MOS transistor is connected to a source of the first MOS transistor, a drain of the third MOS transistor is connected to a drain of the first MOS transistor, and a gate of the third MOS transistor is configured to receive an adjusting signal. The embodiments of the disclosure facilitate enlarging the range of an effective recognition window of the data signal.