Memory Receiver Reference Voltage Tuning for RMT Signal Windows
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Solution Overview
Problem
In high-speed memory testing, signal quality deterioration leads to a shrinkage of the maximum data signal recognition window, which existing equalizers like CTLE and DFE struggle to enlarge effectively.
Innovation Solution
A receiver circuit utilizing MOS transistors, including a signal receiving circuit with first and second MOS transistors to compare voltage magnitudes and an adjusting circuit with a third MOS transistor, which fine-tunes the reference signal to enlarge the data signal recognition window by controlling the conductive current and voltage values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed data transmission is implemented, then transmission speed is improved, but signal quality deteriorates causing the data signal recognition window to shrink
Solution Approach 1:
The patent changes the voltage parameter of the reference signal dynamically. By adjusting the voltage value of the reference signal according to the data signal characteristics, the comparison window is optimized to maintain signal recognition accuracy at high speeds. The voltage adjustment allows the receiver to adapt to signal quality variations while maintaining high transmission speed.
2Reliability
If CTLE or DFE equalizers are used to enlarge the recognition window, then signal quality is improved, but device complexity increases
Solution Approach 1:
The patent extracts the essential function of equalization (enlarging the recognition window) and implements it through a simplified voltage adjustment mechanism rather than complex CTLE or DFE equalizer circuits. By taking out only the necessary voltage control function and implementing it through simple transistor-based circuits, the patent achieves equalization效果 without the complexity of traditional equalizers.
Solution Approach 2:
The patent introduces a reference signal with adjustable voltage as an intermediary between the data signal and the comparison circuit. This intermediary allows flexible adjustment of the comparison window to match signal characteristics, achieving adaptive equalization without requiring complex equalizer circuits. The reference signal acts as a mediator that simplifies the overall system complexity.
3Adaptability or versatility
If the reference signal voltage is adjusted to enlarge the recognition window, then the data signal recognition capability is improved, but the precision of voltage adjustment must be maintained
Solution Approach 1:
The patent implements self-service through automatic voltage adjustment based on detected signal characteristics. The system automatically adjusts the reference signal voltage to optimize the recognition window without requiring external manual calibration. This self-adjusting mechanism maintains voltage precision while providing adaptability to different signal conditions.
Solution Approach 2:
The patent employs feedback mechanisms where the comparison result is used to adjust the reference signal voltage. By monitoring whether the data signal is correctly recognized and adjusting the reference voltage accordingly, the system maintains optimal recognition window precision while adapting to different signal conditions. The feedback loop ensures both adaptability and precision are maintained.
Data Source
AI summary
A receiver includes the following: a signal receiving circuit, including a first MOS transistor and a second MOS transistor, where a gate of the first MOS transistor is configured to receive a reference signal and a gate of the second MOS transistor is configured to receive a data signal, and the signal receiving circuit is configured to output a comparison signal, the comparison signal being configured to represent a magnitude relationship between a voltage value of the reference signal and a voltage value of the data signal; and an adjusting circuit, including a third MOS transistor, where a source of the third MOS transistor is connected to a source of the first MOS transistor, a drain of the third MOS transistor is connected to a drain of the first MOS transistor, and a gate of the third MOS transistor is configured to receive an adjusting signal.