Memory Receiving Circuit Signal Processing
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Solution Overview
Problem
Memory devices face challenges in operating with fast read/write operations and low power consumption while effectively removing inter-symbol interference and noise from received signals, especially in high-speed serial links where residual signals cause errors.
Innovation Solution
A receiving circuit with a summing circuit and decision feedback equalizer that processes signals by subtracting held signals from current signals, using clock signals with different phases to reduce inter-symbol interference and noise, and outputting equalized data robust against noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional receiving circuits are used in high-speed serial links, then operation speed can be maintained, but inter-symbol interference and noise cause signal errors and reduced reliability
Solution Approach 1:
The receiving circuit is segmented into multiple parallel paths: a first path that directly transmits the received signal, a second path that holds the received signal, and a third path that processes the held signal. This segmentation allows different processing operations to occur simultaneously on the same signal, enabling interference cancellation without compromising operation speed.
Solution Approach 2:
A summing circuit acts as an intermediary that combines the direct signal from the first path with the processed signal from the third path. This intermediary component enables the integration of multiple signal versions, allowing the circuit to reconstruct the original signal by canceling out inter-symbol interference and noise components.
2Reliability
If signal processing operations are performed to remove interference, then signal reliability improves, but circuit complexity increases
Solution Approach 1:
Multiple signal processing functions are merged into a unified receiving circuit structure. The first path, second path, third path, summing circuit, and decision feedback equalizer are integrated to work together in parallel, combining interference cancellation, signal processing, and equalization functions into a single cohesive system that achieves high reliability without requiring separate independent circuits.
Solution Approach 2:
The receiving circuit is designed with multi-functionality, where the same circuit structure handles multiple tasks simultaneously: direct signal transmission, signal holding, interference processing, summing, and equalization. This universal design allows a single circuit to perform what would traditionally require multiple specialized circuits, reducing overall system complexity.
3Speed
If fast read/write operations are implemented, then operation speed increases, but susceptibility to noise and interference increases
Solution Approach 1:
The circuit performs preliminary signal processing by creating and processing a held version of the received signal before final decision-making. The second path holds the received signal, and the third path processes this held signal to predict and cancel interference components before they affect the final data recovery, enabling fast operations with noise immunity.
Solution Approach 2:
A decision feedback equalizer is implemented that uses feedback from previously decided data to improve current signal decisions. The equalizer uses the held and processed signal along with feedback from prior decisions to cancel inter-symbol interference and noise, allowing the circuit to maintain high-speed operation while being robust against noise through continuous feedback adjustment.
Data Source
AI summary
A memory device including a receiving circuit is provided. The receiving circuit of the memory device includes a first path receiving a received signal and outputting the received signal directly as a first corrected signal in a current clock signal, a second path holding or tracking the received signal and outputting a second corrected signal in the current clock signal, wherein the second corrected signal is held in a previous clock signal, a summing circuit summing the first corrected signal and the second corrected signal and outputting a summed received signal, and a decision feedback equalizer comparing the summed received signal with a reference signal to decide equalized data and outputting the equalized data in the current clock signal.