Memory Redirection Circuit for Defective Row Bypass
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Solution Overview
Problem
Existing memory technologies face inefficiencies in implementing row or column redundancy in data arrays, particularly in smaller geometries, leading to increased manufacturing costs and defective rows/columns, where static multiplexers do not operate effectively due to separate decoding and control circuitry requirements.
Innovation Solution
A data entry redirection circuit is introduced in a second data access path to redirect memory access requests from defective rows/columns to redundant ones before actual data access, maintaining low latency by performing the redirection outside the primary data access path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If memory is provided in smaller geometries to reduce semiconductor packaging size, then packaging size is reduced, but manufacturing yield decreases and the number of defective rows/columns increases
Solution Approach 1:
The patent pre-configures redundant rows and columns within each sub-array during the design phase, before manufacturing defects are known. This preliminary preparation allows the memory system to immediately redirect access from defective rows/columns to redundant ones without requiring complex runtime decision-making, thereby maintaining high reliability despite smaller geometry constraints
Solution Approach 2:
The patent implements redundancy at the sub-array level rather than globally across the entire memory array. Each sub-array has its own dedicated redundant rows and columns, allowing localized defect compensation without affecting the entire memory system. This local approach enables efficient use of redundancy resources while maintaining overall manufacturing yield
2Reliability
If static multiplexers are used for row/column redundancy, then defective rows/columns can be bypassed, but device complexity increases due to separate decoding and control circuitry requirements
Solution Approach 1:
The patent merges the redundancy management function into the existing sub-array decoder circuitry. Instead of using separate static multiplexers with dedicated control logic, the patent modifies the row and column decoders to directly generate redirected addresses when defects are detected. This integration eliminates the need for separate multiplexer systems and their associated control circuitry, significantly reducing device complexity while maintaining defect bypass capability
Solution Approach 2:
The patent makes the sub-array decoder circuitry multi-functional by enabling it to perform both normal address decoding and defect redirection functions. The same decoder logic that normally translates row/column addresses is also capable of detecting defective addresses and automatically redirecting to redundant rows/columns. This universal approach eliminates the need for dedicated redundancy management circuitry
3Reliability
If redundant rows/columns are designed within each sub-array, then defect coverage is improved, but area overhead increases
Solution Approach 1:
The patent implements a partial redundancy strategy where only certain rows and columns within each sub-array are designated as redundant, rather than providing complete redundancy for all possible defects. This selective approach provides sufficient defect coverage for typical manufacturing variations while minimizing the area overhead associated with redundant circuitry
Solution Approach 2:
The patent divides the memory array into multiple sub-arrays, each with its own localized redundant rows and columns. This segmentation allows the redundancy overhead to be distributed across multiple smaller units rather than concentrated in a single large redundant section. Each sub-array's redundancy serves only that sub-array, reducing the total area overhead compared to a global redundancy approach
Data Source
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AI summary
Embodiments disclosed include redirecting data from a defective data entry in memory to a redundant data entry prior to data access. Related systems and methods are also disclosed. The memory is configured to receive a memory access request. The received memory access request comprises a data entry address. The memory uses the data entry address to access data stored in a data array in the memory in a first data access path. It is possible that the rows or columns in the memory may be defective as a result of a manufacturing process. In the event that a row or column at the data entry address in the data array is defective, a data entry redirection circuit redirects the memory access request to a redundant row or column in the data array prior to data access.