Non-volatile Memory Programming Using Reduced Verification Voltages

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional non-volatile memory devices face challenges in reducing programming periods while maintaining acceptable bit error rates, particularly with multi-level memory cells, due to increased verification voltages and adjacent cell coupling effects.

Innovation Solution

A method and system that define a reduced set of verification voltages for multi-level memory cells, using incremental step pulse programming (ISPP) with a target verification voltage and extra pulses to minimize programming time and bit error rate, by applying a set of verification voltages and ISPP pulses based on calculated extra pulses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the number of verification voltages is increased to accurately verify each programmable data state, then the bit error rate is reduced, but the programming period is increased

Engineering Contradiction:

Improvebit error rateVSAvoidprogramming period

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial verification by selecting only a subset of verification voltages from the full set of programmable data states. Instead of verifying all possible states, the method verifies only those states that are relevant to the current programming operation and adjacent cell coupling effects, thereby reducing the programming period while maintaining acceptable bit error rates

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The patent changes the verification parameter from verifying all data states to verifying only a selected subset of states. The method dynamically adjusts which verification voltages are applied based on the programming context, transforming the verification process from a comprehensive check to a targeted verification approach that reduces time while maintaining reliability

Inventive Principle:

Principle #35Parameter changes

2Manufacturing precision

If pre-equalization programming techniques are used to reduce adjacent cell coupling effects, then the programming accuracy is improved, but the number of verification voltages required increases

Engineering Contradiction:

Improveprogramming accuracyVSAvoidnumber of verification voltages

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies pre-equalization programming techniques to compensate for adjacent cell coupling effects before the main programming operation. By pre-compensating the threshold voltage of memory cells that will be affected by subsequent programming operations, the method improves programming accuracy while managing the complexity of verification voltages through selective verification

Inventive Principle:

Principle #10Preliminary action

3Reliability

If the number of programming steps is increased to reduce adjacent cell coupling effects, then the data integrity is improved, but the programming period is increased

Engineering Contradiction:

Improvedata integrityVSAvoidprogramming period

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the programming process into multiple steps with different verification strategies. By dividing the programming operation into phases where different numbers of verification voltages are applied at different stages, the method maintains data integrity through comprehensive verification when needed while reducing the overall programming period through optimized verification at other stages

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the programming period and bit error rate by optimizing the number of verification voltages and pulses, thereby enhancing data storage efficiency and reliability in non-volatile memory devices.

Implementation Method 1

a sequence of high-voltage pulses having variable levels (e.g., sequentially increasing) is applied to the control gate of the memory cell in order to adjust its threshold voltage. Such programming methods are commonly referred to as 'incremental-step pulse programming' or 'ISPP'

Methodology Applied

Scientific EffectIncremental-step pulse programming:

Data Source

PatentUS9202576B2Non-volatile memory device and programming method using fewer verification voltages than programmable data states

Publication Date: 2015.12.01 SAMSUNG ELECTRONICS CO LTD

AI summary

A method of programming a non-volatile memory device includes; defining a set of verification voltages, setting a maximum verification voltage among verification voltages that are less than or equal to a first target programming voltage to be a target verification voltage, calculating a number of extra pulses based on the target verification voltage and the first target programming voltage, verifying whether a threshold voltage of the memory cell is equal to or greater than the target verification voltage by applying an incremental step pulse program (ISPP) pulse to the memory cell and then applying at least one verification voltage in the set of verification voltages to the memory cell, and further applying the ISPP pulse to the memory cell a number of times equal to the number of extra pulses when the threshold voltage is verified to be equal to or greater than the target verification voltage.