Memory Device With Reduced Programming Voltage
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Solution Overview
Problem
Conventional nonvolatile memory devices face challenges in reducing writing and erasing voltages, and achieving high memory density through multi-level storage due to limitations in insulation film thickness and gate length reduction.
Innovation Solution
A memory device with a semiconductor region having an equivalent sectional radius equal to or smaller than the equivalent oxide film thickness, allowing for reduced writing and erasing voltages while maintaining memory retention characteristics, and enabling stable multi-level storage by regulating the gate length and equivalent sectional radius to set a unique multi-level interval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate length is reduced to increase memory density, then the operating voltage decreases, but the writing and erasing voltages remain high and cannot be reduced
Solution Approach 1:
The patent divides the semiconductor region into multiple fine cross-sectional regions (first semiconductor region, second semiconductor region, etc.) arranged in parallel. Each region has its own memory means and shares a common gate, enabling the gate to control multiple segmented regions simultaneously. This segmentation allows reduction of writing/erasing voltage while maintaining memory density through parallel structure.
Solution Approach 2:
The patent transitions from a conventional planar structure to a three-dimensional structure where semiconductor regions are arranged vertically with fine cross-sections. The equivalent sectional radius constraint (r ≤ tm) creates a unique geometric relationship between the horizontal dimension (cross-sectional radius) and vertical dimension (insulation film thickness), enabling voltage reduction through dimensional optimization.
2Speed
If the insulation film thickness is reduced to improve writing speed, then the writing voltage decreases, but memory retention characteristics deteriorate
Solution Approach 1:
The patent changes the geometric parameter of the semiconductor region from a conventional planar shape to a fine cross-sectional shape with equivalent radius r ≤ tm. This parameter change creates a unique electric field distribution that enables simultaneous achievement of fast writing (through adequate field strength) and good retention (through controlled field penetration), resolving the trade-off between writing speed and memory retention.
3Productivity
If multi-level storage is implemented to increase memory density, then the number of stored values increases, but it becomes difficult to clearly separate and write between multi-levels
Solution Approach 1:
The patent applies local quality by creating unique electric field characteristics in each segmented semiconductor region through the fine cross-sectional geometry. This localized field control enables precise manipulation of charge distribution in different regions, facilitating clear separation and distinct writing of multiple storage levels while maintaining high density through parallel segmented structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces writing and erasing voltages to approximately 70% of conventional levels, improves memory retention, and enables stable multi-level storage with a unique gate voltage interval, enhancing memory density and operation efficiency.
Implementation Method 1
a memory device which can reduce the voltage for writing or erasing
Data Source
AI summary
A memory device (1) includes at least a first semiconductor region (100) having a length, a first surface, and a cross section surrounded by the first surface, a memory means (300) provided on the first surface, and a gate (400) provided on the memory means (300), and an equivalent sectional radius of the cross section of the first semiconductor region (100) is set to be equal to or smaller than an equivalent silicon oxide film thickness of the memory means (300) to realize low program voltage. The equivalent sectional radius r of the cross section is set to be 10 nm or less and the gate length is set to be 20 nm or less so that multi-level interval converted to gate voltage becomes a specific value which can be identified under the room temperature.