Semiconductor Memory Redundancy Repair via Address Reassignment
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently managing redundancy to minimize size increase while correcting defective memory cells, as adding redundancy blocks typically enlarges the memory chip and may not detect errors effectively during the manufacturing process.
Innovation Solution
A repair control circuit is implemented to replace a fail cell in a memory block with a normal cell from the same block and then replace that normal cell with a redundancy cell, allowing for efficient use of redundancy resources without significant size increase, by reassigning addresses and utilizing redundancy cells for data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy memory blocks are added to correct defective memory cells, then reliability is improved, but the overall size of the memory chip increases
Solution Approach 1:
The patent implements a nested repair structure where a first normal memory cell is used to repair a defective cell, and then a redundancy memory cell is used to repair the first normal memory cell. This nested approach allows the redundancy block to serve multiple repair purposes, maximizing the utilization of redundancy resources while minimizing the required redundancy capacity and overall chip size.
Solution Approach 2:
The patent dynamically changes address parameters through repair control circuits that modify column addresses and word line selections. By changing address parameters, the system can redirect access to repaired cells without requiring additional physical memory space, thus maintaining reliability while controlling chip size.
2Productivity
If multiple repair operations are performed using normal cells from the same block, then redundancy resource efficiency is improved, but the complexity of address management increases
Solution Approach 1:
The patent introduces a repair control circuit as an intermediary between the memory controller and the memory blocks. This intermediary handles the complex address management and repair logic, allowing the normal memory cells to be efficiently utilized for repair operations while isolating the complexity from the rest of the memory system.
Solution Approach 2:
The patent segments the repair process into distinct stages: first using normal cells from the same block for repair, then using redundancy cells for subsequent repairs. This segmentation allows each stage to be optimized independently, improving overall redundancy resource efficiency while managing complexity through structured processing.
Data Source
AI summary
A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.