Semiconductor Memory Redundancy Address Segmentation
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Solution Overview
Problem
As semiconductor memory devices increase in storage capacity, the larger address sizes pose challenges in efficient access and redundancy management, leading to delays and reduced operating speed.
Innovation Solution
The semiconductor memory device employs a redundancy area to replace failing memory cells, using a dual-row address input method where the first row address includes redundancy information, allowing for pre-determination of redundancy operations before active commands, thereby reducing delay times and enhancing operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the storage capacity of the semiconductor memory device is increased, then the address size increases, but the access time increases and operating speed decreases
Solution Approach 1:
The patent divides the row address into two separate parts: a first row address (R0) that is processed early for redundancy determination, and a second row address (R1) that completes the full address specification. This segmentation allows the redundancy check to begin before the complete address is available, overlapping operations to reduce total access time while supporting larger address spaces.
2Quantity of substance
If the storage capacity of the semiconductor memory device is increased, then the address size increases, but the redundancy determination time increases
Solution Approach 1:
The patent performs preliminary redundancy determination using only the first row address (R0) before the second row address (R1) is fully received. The judgment circuit evaluates whether redundancy replacement is needed based on the partial address information available early in the access cycle, allowing this determination to be made in advance rather than waiting for the complete address.
3Speed
If a dual-row address input method is used for early redundancy determination, then the operating speed improves, but the device complexity increases
Solution Approach 1:
The judgment circuit is designed to handle multiple functions: it can perform redundancy determination based on the first row address (R0) alone for early detection, and also perform complete redundancy determination when both first (R0) and second (R1) row addresses are available. This multi-functionality allows the same circuit to operate efficiently across different address sizes and access modes without requiring separate dedicated circuits for each function.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes first word lines connected to a memory cell array, second word lines connected to a redundancy area, a first row decoder configured to perform selecting from the first word lines based on a row address, a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address, and a second row decoder configured to perform selecting from the second word lines. The row address includes a first row address and a second row address input in order in a time-sharing method. The first row address includes all of the redundancy address.