Memory Redundancy for Single Bit Failure Correction
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Solution Overview
Problem
Existing redundancy schemes in semiconductor memories are less effective in addressing scattered single bit failures, as they often require replacing large redundant elements for single bit failures, which is inefficient.
Innovation Solution
Implementing a set of predetermined columns of bits to address failures in any row, allowing for the replacement of single bit failures with redundant bits, thereby reducing power consumption by lowering the voltage applied to the memory array, which is particularly effective in reducing single bit failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large redundant elements are used to replace bit failures, then reliability is improved for group failures, but device complexity increases and effectiveness decreases for scattered single bit failures
Solution Approach 1:
The patent divides the redundancy approach into two distinct segments: column redundancy for handling row failures and bit redundancy for handling column failures. This segmentation allows each redundancy mechanism to be optimized for its specific failure pattern, avoiding the need for oversized redundant structures that would be required if a single unified approach was used for all failure types.
Solution Approach 2:
The patent applies different redundancy strategies to different locations and failure patterns within the memory array. Column redundancy is applied to protect against row failures, while bit redundancy is applied to protect against column failures. This localized approach ensures that redundancy resources are allocated efficiently based on the specific protection needs of different memory regions and failure modes.
2Reliability
If large redundant elements are used to replace single bit failures, then reliability is improved, but the efficiency of redundancy decreases
Solution Approach 1:
The patent segments redundancy into column-level and bit-level mechanisms, allowing bit redundancy to specifically address single bit failures without requiring the overhead of large redundant elements. This segmentation enables efficient redundancy utilization where only the necessary redundancy resources are activated for the specific failure type being corrected.
Solution Approach 2:
The patent applies partial redundancy by using bit redundancy (a single redundant bit per column) specifically for correcting single bit failures, rather than applying full column redundancy (which would require replacing entire columns) for all failure types. This partial approach provides sufficient protection for the most common failure mode while minimizing the overhead for less frequent failure patterns.
3Use of energy by moving object
If voltage is reduced to lower power consumption, then energy efficiency is improved, but single bit failures increase
Solution Approach 1:
The patent implements redundancy mechanisms (column redundancy and bit redundancy) as a protective cushion that compensates for the increased failure rate caused by voltage reduction. By having redundant bits and columns pre-positioned in the memory array, the system can correct single bit failures that occur during low-voltage operation, thereby enabling aggressive voltage scaling for power savings without unacceptable reliability degradation.
Data Source
AI summary
Structures for substituting single bits in an array may include a first array having a plurality of word lines, and for each of the plurality of word lines a memory operable to store a bit substitution column value, and a first data output line operable to communicate the bit substitution column value to a write data shifter. The bit substitution column value may be associated with a bit substitution column in a second array, and the write data shifter may be operable to substitute the bit by shifting data to a redundancy column in the first array.