Semiconductor Memory Redundancy Circuit for Cell Failure Repair
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Solution Overview
Problem
The increasing integration density in semiconductor devices leads to higher failure rates of memory cells, reducing fabrication yield and necessitating novel designs to ensure reliable data transmission, especially as faster data transmission speeds increase error probabilities.
Innovation Solution
A semiconductor system comprising a first and second semiconductor device, where the second device can repair addresses by storing data in redundancy areas or correcting errors in normal areas based on retention characteristics of memory cells, using a command, address, and retention information signals to manage data storage and output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density is increased to improve productivity, then productivity is improved, but reliability deteriorates due to higher failure rates of memory cells
Solution Approach 1:
The memory address space is segmented into normal areas and redundancy areas. When a memory cell fails, its address is stored in a failure address storage circuit, and future accesses to that address are redirected to corresponding redundancy memory cells. This segmentation allows the system to maintain high integration density while isolating and managing failures in specific segments without affecting the entire memory array.
Solution Approach 2:
The system dynamically changes the operational parameters by switching between normal memory cells and redundancy memory cells based on detected failures. When a failure is detected, the system modifies the address mapping parameter through the failure address storage circuit, redirecting accesses from failed cells to redundant cells, thereby maintaining reliability without reducing integration density.
2Productivity
If data transmission speed is increased to improve productivity, then productivity is improved, but reliability deteriorates due to increased error probability
Solution Approach 1:
The system implements feedback through the failure address storage circuit that continuously monitors memory cell operations. When errors occur during high-speed data transmission, the feedback mechanism detects the failure, stores the faulty address, and redirects subsequent accesses to redundancy cells, thereby maintaining data transmission reliability even at high speeds.
Solution Approach 2:
Redundancy memory cells are prepared in advance and remain idle during normal operations. When a failure occurs during high-speed transmission, the preliminary-prepared redundancy cells can immediately take over without interrupting the data transmission flow, thus maintaining both high speed and reliability.
3Reliability
If redundancy memory cells are added to improve reliability, then reliability is improved, but device complexity increases
Solution Approach 1:
The redundancy memory cells serve multiple functions: they can replace failed memory cells at any location in the memory array, and the failure address storage circuit can store multiple failure addresses. This multi-functionality allows a single redundancy structure to handle various failure scenarios, improving reliability without proportionally increasing device complexity.
Solution Approach 2:
The failure address storage circuit acts as an intermediary between the memory address input and the memory array. It intercepts address signals, compares them against stored failure addresses, and redirects to redundancy cells when necessary. This intermediary approach manages the complexity of reliability mechanisms separately from the core memory structure, allowing the memory array itself to remain relatively simple.
4Reliability
If error detection and correction mechanisms are implemented to improve reliability, then reliability is improved, but device complexity increases
Solution Approach 1:
The error handling functionality is extracted from the main data transmission path and implemented as a separate failure address storage circuit. This circuit independently monitors and manages errors without interfering with the high-speed data transmission flow, thereby improving reliability while minimizing the impact on device complexity and maintaining transmission performance.
Data Source
AI summary
A semiconductor device may be provided. The semiconductor device may include a memory area. The memory area may be configured to compare an address with a first failure address and a second failure address to store an input datum into a redundancy area and to output the stored input datum as an output datum or configured to compare the address with the first and failure addresses to correct an error of an input datum stored in a normal area to output the corrected input datum as the output datum. The semiconductor device may include a failure address storage circuit. The failure address storage circuit may be configured to store the address as a first failure address based on a first retention information signal and configured to store the address as a second failure address based on a second retention information signal.