Nonvolatile Memory Redundancy Cell Region for Column Repair
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Solution Overview
Problem
The increasing integration of semiconductor memory devices leads to a higher number of defective memory cells, reducing yield and performance, as existing technologies struggle to efficiently utilize redundancy cells and correct errors in nonvolatile memory devices.
Innovation Solution
A storage device with a nonvolatile memory device and a memory controller that includes a redundancy cell region for repairing defective columns, using an ECC engine to generate parity data and perform column repairs, and selectively using defective column address information for ECC decoding to enhance error correction efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the integration degree of semiconductor memory devices is increased to increase memory capacity, then the memory capacity is improved, but the number of defective memory cells increases and yield decreases
Solution Approach 1:
The memory cell array is divided into normal cell regions and redundancy cell regions. The redundancy cell region is further segmented into first redundancy cell regions (coupled to first bit-lines) and second redundancy cell regions (coupled to second bit-lines), allowing targeted repair of defective columns while preserving functional memory capacity.
Solution Approach 2:
The system changes the operational parameters by dynamically selecting which bit-lines to repair based on defect detection. When first bit-lines are defective, column repair is performed using first redundancy cell regions; when second bit-lines are defective, column repair uses second redundancy cell regions, optimizing yield maintenance.
2Reliability
If redundant memory cells are used to repair defective memory cells, then defective cells are repaired, but the usability of redundancy cell region is limited
Solution Approach 1:
The redundancy cell region is designed to serve multiple functions: it can repair defective columns in the normal cell region, store parity data for ECC operations, and provide backup capacity. This multi-functionality significantly increases the usability of the redundancy cell region beyond traditional single-purpose repair.
Solution Approach 2:
The system adds a new dimension to redundancy cell usage by implementing dual sets of redundancy cells (first and second redundancy cell regions) coupled to different bit-line sets. This dimensional expansion allows the redundancy region to handle both normal cell repairs and parity data storage simultaneously.
3Reliability
If column repair is performed on defective bit-lines, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The address decoder is segmented to independently decode addresses for first bit-lines and second bit-lines separately. This segmentation allows selective column repair operations on specific defective bit-line sets without affecting the entire memory array, reducing the operational complexity of the repair mechanism.
Solution Approach 2:
The address decoder acts as an intermediary that manages the complexity of column repair operations. It translates logical addresses into physical bit-line selections, automatically routing repair operations to the appropriate redundancy cell region based on which bit-lines are defective, thereby simplifying the overall control logic.
4Productivity
If additional column addresses are assigned to defective bit-lines and redundancy bit-lines, then parity data storage is optimized, but address management complexity increases
Solution Approach 1:
Additional column addresses are pre-assigned to both defective bit-lines and second bit-lines before parity data is stored. This preliminary address assignment allows the parity data to be stored in predetermined locations (second redundancy cell regions) without requiring complex runtime address calculation or dynamic address mapping.
Solution Approach 2:
The address management system applies different address mapping rules to different regions: normal columns use standard addressing, first defective bit-lines use column repair addressing with additional column addresses, and second bit-lines use redundancy addressing. This localized quality approach optimizes parity storage while managing complexity through region-specific rules.
Data Source
AI summary
A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.