Memory Redundancy Control Circuit for Defect Relief
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Solution Overview
Problem
As memory devices, such as resistance change type memories, experience increased storage density and miniaturization, the percentage of defective elements rises, leading to a significant increase in the circuit scale required for redundancy functions, which can be cumbersome and inefficient.
Innovation Solution
The implementation of a memory device with a fuse circuit that stores defect addresses and a control circuit that manages redundancy data, allowing selective transfer and comparison of redundancy data based on addresses to determine whether to replace defective columns with redundancy columns, thereby reducing the circuit scale and improving defect relief efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy functions are expanded to handle increased defective elements, then defect relief capability is improved, but circuit scale increases significantly
Solution Approach 1:
The patent divides the memory cell array into multiple blocks, with each block having its own redundancy control circuit. This segmentation allows the redundancy function to be distributed across smaller, more manageable circuits rather than requiring a single large-scale redundancy control circuit, thus improving defect relief capability while controlling circuit scale.
Solution Approach 2:
The patent implements preliminary testing of memory cells during manufacturing to identify defective elements before the memory device is put into service. Defect addresses are stored in a fuse circuit, and redundancy control circuits are pre-configured to replace defective columns with redundancy columns. This preliminary action enables efficient defect relief without requiring large-scale redundancy circuits to be activated during normal operation.
2Reliability
If redundancy columns are added to replace defective columns, then defect relief efficiency is improved, but chip size increases
Solution Approach 1:
The patent applies redundancy columns locally only to the extent necessary to replace defective columns within specific blocks. Rather than adding redundancy columns across the entire chip, the redundancy structure is concentrated in specific local areas where defects occur, thus improving defect relief efficiency while minimizing the overall increase in chip size.
Solution Approach 2:
The patent implements redundancy columns as a partial solution, adding redundancy only where and to the extent necessary to handle defective elements. The redundancy control circuit is designed to activate redundancy columns selectively based on stored defect addresses, avoiding the need for excessive redundancy across the entire chip and thus controlling chip size growth.
3Adaptability or versatility
If fuse circuit stores defect addresses for all blocks, then defect management capability is improved, but circuit complexity increases
Solution Approach 1:
The patent segments the defect management function by implementing separate fuse circuits and redundancy control circuits for each block. Each block's fuse circuit stores defect addresses specific to that block, and the corresponding redundancy control circuit manages redundancy replacement for that block. This segmentation improves defect management capability for each block while controlling overall circuit complexity through modular architecture.
Data Source
AI summary
According to one embodiment, a memory device includes: a memory cell array including a first and a second array; a fuse circuit to hold first data; and a control circuit to control a replacement process on the first and second arrays based on the first data. When a first address in a first direction in the first array is supplied, the fuse circuit transfers the first data corresponding to the first address to the control circuit, and when a second address in a second direction in the first array is supplied after the first data is transferred, the control circuit accesses one of the first and second arrays based on a comparison result for the second address and the first data.