Semiconductor Memory Redundancy via Dummy Cell Arrays
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Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining sufficient capacitance and replacing defective memory cells without increasing device size, especially as defects occur in a small number of cells, leading to yield loss and vulnerability to noise in open bit line architectures.
Innovation Solution
The semiconductor memory device employs a redundancy memory cell array and unused dummy memory cell arrays to replace defective memory cells, activating multiple redundancy word lines to ensure sufficient capacitance and maintain the same number of replacements as prior art, without increasing device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy memory cells are provided to replace defective memory cells, then reliability is improved, but device size increases
Solution Approach 1:
The patent makes unused dummy memory cell arrays serve dual purposes: they function as dummy arrays during normal operation and as redundancy memory cell arrays when defects occur. By activating specific word lines in these dummy arrays, the system can replace defective memory cells without adding dedicated redundancy arrays, thus maintaining device size while improving reliability.
Solution Approach 2:
The patent recovers and reuses the previously wasted dummy memory cell arrays. Instead of discarding these unused arrays as non-functional elements, the system activates them as redundancy resources when defects are detected, thereby converting wasted space into useful replacement capacity without increasing overall device size.
2Area of stationary object
If open bit line architecture is used, then device size is reduced, but vulnerability to noise increases
Solution Approach 1:
The patent introduces dummy memory cell arrays as intermediary elements that serve as noise references. These dummy arrays are activated alongside normal memory cell arrays and provide reference signals that help sense amplifiers distinguish actual data signals from noise, thereby reducing noise vulnerability in the compact open bit line architecture.
3Reliability
If multiple redundancy word lines are activated, then sensing margin is improved, but device complexity increases
Solution Approach 1:
The patent pre-organizes the dummy memory cell arrays with word line structures that can be independently activated. This preliminary arrangement allows the system to selectively activate one or more specific word lines in the dummy arrays as redundancy resources without requiring complex real-time reconfiguration, thereby improving sensing margin while keeping control complexity manageable.
Data Source
AI summary
A semiconductor memory device includes a plurality of memory cell mats each comprising a plurality of normal memory cell arrays; and a redundancy memory cell array configured to replace a defective memory cell with a plurality of redundancy memory cells corresponding to a redundancy word line when the redundancy word line corresponding to one or more redundancy memory cell arrays is activated in response to an address corresponding to the defective memory cell among the plurality of normal memory cell arrays.