Nonvolatile Memory Redundancy Switching via Erase-Time Detection
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Solution Overview
Problem
Nonvolatile semiconductor memories face challenges in efficiently replacing defective cells with redundant cells during the data erase process, leading to prolonged test times and high costs due to the need for extensive screening, often resulting in usable redundant cells being overlooked, thus considering defective products.
Innovation Solution
A nonvolatile semiconductor memory system that includes a cell array, a redundancy array, an erase circuit, a timer, and a controller to automatically detect and replace defective cells with redundant cells by measuring elapsed time during erase operations, ensuring efficient use of redundant cells and reducing test costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If extensive screening is performed to detect defective cells, then defect replacement accuracy is improved, but test time increases
Solution Approach 1:
The memory device performs self-diagnosis by monitoring its own erase operation timing. The controller detects erase failures by comparing actual erase completion time against expected time thresholds, enabling the device to identify defective cells without external screening intervention.
Solution Approach 2:
The patent replaces manual/extensive screening processes with an automated timing-based detection system. Instead of performing comprehensive cell-by-cell screening, the system uses timer measurements during erase operations to automatically identify defective cells, substituting a complex mechanical screening process with a simpler temporal measurement approach.
2Measurement precision
If extensive screening is performed to detect defective cells, then defect replacement accuracy is improved, but test cost increases
Solution Approach 1:
The memory device performs self-diagnosis by monitoring its own erase operation timing. The controller detects erase failures by comparing actual erase completion time against expected time thresholds, enabling the device to identify defective cells without external screening intervention.
Solution Approach 2:
The patent replaces manual/extensive screening processes with an automated timing-based detection system. Instead of performing comprehensive cell-by-cell screening, the system uses timer measurements during erase operations to automatically identify defective cells, substituting a complex mechanical screening process with a simpler temporal measurement approach.
3Reliability
If erase operation time is extended to ensure complete erasure, then erase completeness is improved, but productivity decreases
Solution Approach 1:
The controller implements feedback control by monitoring the timing of erase operations. When an erase operation exceeds the expected time threshold, the controller detects this feedback signal and automatically intervenes to replace the defective cell, preventing unnecessary extension of the erase operation while maintaining reliability.
Solution Approach 2:
Instead of extending the erase operation time for all cells to ensure completeness, the system applies the erase operation for a standard duration and only extends or retries for specific cells that show timing anomalies, performing partial additional action only where needed rather than universally.
Data Source
AI summary
A nonvolatile semiconductor memory includes a cell array, redundancy array, erase circuit, timer, and controller. The cell array has a plurality of memory cells. The redundancy array has a plurality of redundant cells capable of replacing the memory cell. The erase circuit performs an erase operation on a target cell including the memory cell or the redundant cell. The timer measures the time elapsed from the start of the erase operation performed for the target cell by the erase circuit. The controller stops the erase operation and replaces the target cell with the redundant cell, when detecting that a predetermined time has elapsed from the start of the erase operation by the measurement of the elapsed time by the timer.