Direct-Input Memory Redundancy for Low-Latency ECC Decoding

Solution Overview

Problem

The existing memory devices face increased latency in error correction operations due to the lengthy data path required for transferring redundant data bits to error correction circuitry, which can delay retrieval operations.

Innovation Solution

Implementing a direct-input redundancy scheme with a dedicated ECC circuit and an adaptive syndrome decoder that reduces the data path length by directly inputting redundancy data into the error correction circuitry, allowing for selective operation based on the type of data being decoded.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If redundant data bits are transferred through the existing data path to error correction circuitry, then error correction can be performed, but propagation delay increases and retrieval operation latency increases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidpropagation delay

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the error correction system into two independent parts: a first error correction circuit dedicated to processing primary data bits and a second error correction circuit dedicated to processing redundant data bits. This segmentation allows each circuit to handle its specific data type through optimized, shorter data paths, reducing overall propagation delay while maintaining complete error correction capability for both data and redundant bits.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a data plane selector as an intermediary component that intelligently routes primary data bits to the first error correction circuit and redundant data bits to the second error correction circuit. This mediator eliminates the need for redundant data to travel through the longer general data path, directly reducing propagation delay while ensuring error correction is performed on the appropriate data type.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If redundant data bits are transferred through the existing data path to error correction circuitry, then error correction can be performed, but retrieval operation latency increases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidretrieval operation speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent segments the error correction system into two independent parts: a first error correction circuit dedicated to processing primary data bits and a second error correction circuit dedicated to processing redundant data bits. This segmentation allows each circuit to handle its specific data type through optimized, shorter data paths, reducing overall propagation delay while maintaining complete error correction capability for both data and redundant bits.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a data plane selector as an intermediary component that intelligently routes primary data bits to the first error correction circuit and redundant data bits to the second error correction circuit. This mediator eliminates the need for redundant data to travel through the longer general data path, directly reducing propagation delay and improving retrieval operation speed.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Loss of time

If a dedicated ECC circuit is used for redundant data, then propagation delay is reduced, but device complexity increases

Engineering Contradiction:

Improvepropagation delayVSAvoidcircuit architecture complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent implements error correction circuits with universal functionality that can process both primary data bits and redundant data bits, depending on configuration. The same error correction algorithm and circuit logic are used for both data types, reducing the need for completely separate complex circuitry while still achieving the benefit of dedicated processing paths through the data plane selector.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent uses parameter changes in the form of control signals and configuration settings that allow the error correction circuits to adapt their operation based on the data type being processed. By changing operational parameters rather than physical circuit configuration, the system achieves dedicated processing for redundant data without permanently increasing hardware complexity.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11016843B2Direct-input redundancy scheme with adaptive syndrome decoder

Publication Date: 2021.05.25 MICRON TECHNOLOGY INC

AI summary

Methods, systems, and devices for operating memory cell(s) using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. An output of the error correction circuit may be used to generate syndrome bits, which may be decoded by a syndrome decoder. The syndrome decoder may indicate whether a bit of the data should be corrected by selectively reacting to inputs based on the type of data to be corrected. For example, the syndrome decoder may react to a first set of inputs if the data bit to be corrected is a regular data bit, and react to a second set of inputs if the data bit to be corrected is a redundant data bit.