Memory System Redundancy Word Line Refresh Control

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Solution Overview

Problem

Memory cells experience data loss due to current leakage at PN junctions of MOS transistors, leading to charge loss in capacitors, and word line disturbances cause data loss in adjacent memory cells when highly active word lines are frequently activated and precharged.

Innovation Solution

A memory system with redundancy word lines and a control unit that periodically refreshes word lines and redundancy word lines based on activation frequency and count, using target and redundancy refresh signals to prevent data loss by selectively refreshing adjacent word lines and redundancy word lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If word lines are frequently activated and precharged to access memory cells, then memory access speed is improved, but data loss in adjacent memory cells occurs due to coupling effects and electronic waves

Engineering Contradiction:
Improvememory access speedVSAvoiddata integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by performing refresh operations on adjacent word lines before data loss can occur. The memory controller detects highly active word lines and proactively refreshes adjacent word lines that are susceptible to coupling effects and electronic wave interference, preventing data loss before it happens.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by monitoring word line activation frequencies and using this information to determine which adjacent word lines need refreshing. The memory controller counts activation times of word lines and uses this feedback to selectively refresh adjacent word lines, creating a closed-loop system that adapts to actual usage patterns.

Inventive Principle:
Principle #23Feedback

2Reliability

If refresh operations are performed on all word lines periodically, then data integrity is maintained, but refresh time and power consumption increase

Engineering Contradiction:
Improvedata integrityVSAvoidrefresh time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies local quality by selectively refreshing only adjacent word lines that are vulnerable to interference from highly active word lines, rather than refreshing all word lines uniformly. This targeted approach maintains data integrity where needed while avoiding unnecessary refresh operations elsewhere, reducing overall refresh time and power consumption.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses partial action by performing refresh operations only on the necessary subset of adjacent word lines that are susceptible to coupling effects, rather than applying excessive refresh operations to all word lines. This optimizes the balance between data protection and resource utilization.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If redundancy word lines are used to replace faulty word lines, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvesystem reliabilityVSAvoidmemory structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent uses copying by creating redundancy word lines that are copies of regular word lines. These redundancy word lines can replace faulty word lines or serve as additional protection against data loss from coupling effects. The copying approach provides a straightforward method for achieving reliability without requiring fundamentally different structural elements.

Inventive Principle:
Principle #26Copying

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The system effectively prevents data loss in memory cells adjacent to highly active word lines and redundancy word lines by implementing targeted refresh operations, minimizing errors caused by word line disturbances and maintaining data integrity.

Implementation Method 1

a capacitor serving to store a charge (data). Depending on whether a charge is stored in the capacitor of the memory cell

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

since current leakage occurs at the PN junction of MOS transistors, the initial charge stored in the capacitor may be lost

Methodology Applied
Scientific EffectCurrent leakage: Electrical Resistance

Implementation Method 3

the voltages of the word lines WLK−1 and WLK+1 are increased and decreased by a coupling effect between the word line WLK and the word lines WLK−1 and WLK+1, thereby influencing charges stored in the cell capacitors

Methodology Applied
Scientific EffectCoupling effect: Capacitance

Implementation Method 4

electronic waves, generated while a word line toggles between the active state and the precharge state, may introduce/discharge electrons into/from a cell capacitor included in a memory cell coupled to an adjacent word line

Methodology Applied
Scientific EffectElectronic waves: Electromagnetic Induction

Data Source

PatentUS9190139B2Memory and memory system including the same
Publication Date: 2015.11.17 SK HYNIX INC
  • US9190139B2 patent drawing
  • US9190139B2 patent drawing
  • US9190139B2 patent drawing

AI summary

A memory may include a plurality of word lines, one or more redundancy word lines for replacing one or more word lines among the plurality of word lines, a target address generation unit suitable for generating one or more target addresses using a stored address, and a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command which is periodically inputted, refreshing a word line selected based on the target address when the refresh command is inputted M times, and refreshing the one or more redundancy word lines whenever the refresh command is inputted N times, wherein the M and N are natural numbers.