Semiconductor Memory Redundancy Repair Mechanism
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in repairing defective memory cells at the package level, requiring external test apparatuses to store and apply defective addresses for programming, which complicates the repair process and increases the burden on the test apparatus.
Innovation Solution
A semiconductor memory device with integrated redundancy address decoders, defective address detection, and programming units that autonomously detect and program defective addresses at the package level, utilizing redundancy memory cell groups and internal control units to manage and correct errors, thereby reducing reliance on external test apparatuses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the address of the defective memory cell is stored in the external test apparatus and applied by the test apparatus to the semiconductor memory device for programming, then the defective memory cell can be repaired, but the repair process becomes complex and the burden on the test apparatus increases
Solution Approach 1:
The patent merges the defective address detection function and the programming function into a single integrated unit within the semiconductor memory device. The defective address detection unit detects defective addresses during test operations, and the defective address program unit receives and programs these addresses during program operations, eliminating the need for external test apparatus to store and apply addresses separately.
Solution Approach 2:
The semiconductor memory device performs self-diagnosis and self-repair by autonomously detecting defective addresses during test operations and programming correction codes without requiring external test apparatus to store or apply the defective addresses. The device serves itself by integrating both detection and programming functions internally.
2Ease of operation
If the semiconductor memory device autonomously detects and programs defective addresses internally, then the repair process is simplified and external intervention is reduced, but the internal device complexity increases
Solution Approach 1:
The patent combines multiple functions (defective address detection, defective address storage, and programming) into integrated units within the semiconductor memory device. The defective address detection unit performs both detection and storage of defective addresses, and the defective address program unit handles programming operations, reducing the need for external apparatus while maintaining operational simplicity.
Solution Approach 2:
The defective address detection unit serves multiple functions: it detects defective addresses during test operations, stores the detected addresses, and outputs them for programming during program operations. This multi-functional design reduces the need for separate dedicated components, balancing internal complexity with operational simplicity.
3Reliability
If multiple redundancy decoders are used to access redundancy memory cell groups, then the repair capability is enhanced, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent divides the memory cell array into multiple memory cell groups and provides corresponding redundancy memory cell groups. Each redundancy decoder is responsible for accessing specific redundancy memory cell groups, creating a segmented architecture that enhances repair capability while managing complexity through organized division of functions.
Solution Approach 2:
The patent provides a predetermined number of redundancy decoders that can access at least one group of redundancy memory cell groups. The system uses more decoders than the minimum single decoder would require, enabling flexible access to multiple redundancy groups and enhancing repair capability for multiple defective addresses while maintaining manageable device complexity.
Data Source
AI summary
A semiconductor memory device may include a memory cell array, a redundancy address decoder, a defective address detection unit, and a defective address program unit. The memory cell array includes a plurality of memory cell groups and a predetermined number of redundancy memory cell groups. The redundancy address decoder includes a predetermined number of redundancy decoders for accessing at least one group of the redundancy memory cell groups when a first defective address is identical to an externally applied address. The defective address detection unit performs a write operation and a read operation on the memory cell array during a test operation to detect a defective address, and outputs the detected defective address as the first defective address when the same defective address is detected a predetermined number of times or more. The defective address program unit receives and programs the first defective address output from the defective address detection unit during a program operation.