Semiconductor Memory Redundancy Cell Dynamic Rerouting
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Solution Overview
Problem
The increasing size of semiconductor memories leads to a higher probability of defective cell occurrences, which limits the flexibility of existing repair methods and results in increased chip size due to the limited redundancy resources and fixed memory density.
Innovation Solution
A memory device with a memory cell array comprising multiple memory cell groups and redundancy memory cell groups, where a data line selection circuit and selection control logic dynamically reroute data paths based on detected defective cells and output data width, allowing for flexible repair of defective cells by utilizing redundancy cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device size increases to meet growing storage demands, then storage capacity is improved, but defective cell occurrence probability increases
Solution Approach 1:
The memory cell array is divided into multiple memory cell groups (first memory cell group, second memory cell group, etc.), each associated with separate data lines. This segmentation allows independent identification and repair of defective cells in specific groups without affecting the entire memory array, thereby maintaining reliability as storage capacity scales up.
Solution Approach 2:
The system dynamically changes operational parameters by selecting different data paths based on detected defective cells. When a defective cell is detected in a particular memory cell group, the system alters the data transmission path to bypass that group using alternative data lines or redundancy cells, thus maintaining reliability while preserving storage capacity.
2Ease of repair
If existing repair methods are used with increased defective cell probability, then repair capability is maintained, but redundancy resources are limited due to fixed repair unit flexibility
Solution Approach 1:
The system employs dynamic repair capabilities where the data line selection circuit can be reconfigured in real-time based on detected defective cells. This dynamic adaptation allows the repair unit to flexibly respond to different defect patterns and locations, significantly enhancing repair unit flexibility beyond fixed repair methods.
Solution Approach 2:
The redundancy memory cell group serves multiple functions: it can replace defective cells from any of the multiple memory cell groups (first, second, etc.), and can be accessed through different data lines. This universal repair capability allows a single redundancy group to handle defects across the entire memory array, maximizing redundancy resource efficiency.
3Device complexity
If a constant group unit of redundancy cells is used for replacement, then redundancy structure is simplified, but the number of replaced redundancy cells increases causing chip size increase
Solution Approach 1:
Instead of using a uniform, constant group unit for all replacements, the system applies local quality by tailoring the repair approach to specific defective cell locations within different memory cell groups. The data line selection circuit enables selective access to redundancy cells based on the specific defect location, optimizing the use of redundancy resources and minimizing the number of redundancy cells needed.
Solution Approach 2:
The system changes the operational parameters of the redundancy structure by dynamically selecting which data lines connect to which memory cell groups based on detected defects. This parameter change allows the same redundancy cells to serve different memory cell groups at different times, reducing the total number of redundancy cells required and thereby reducing chip size.
Data Source
AI summary
In one embodiment, the memory device includes a memory cell array having at least a first memory cell group, a second memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, the second memory cell group includes a plurality of second memory cells associated with a second data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. A data line selection circuit is configured to provide a data path between an input/output node and one of the first data line, the second data and the redundancy data line.