Memory Redundancy Address Replacement for Faulty Word Lines
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Solution Overview
Problem
The increasing complexity of memory devices leads to the production of poor or damaged memory elements, and existing error-correcting code memory technologies face challenges in size reduction and increased production costs.
Innovation Solution
A memory device with a built-in self-test function that includes redundancy address replacement circuits, which replace bad word line addresses detected during a self-test process using redundancy memory blocks, enhancing the reliability of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error-correcting code memory (ECC memory) is used to improve reliability, then reliability is improved, but device complexity and production cost increase
Solution Approach 1:
The patent applies preliminary action by performing a built-in self-test process during manufacturing to detect bad word line addresses before the memory device is shipped. Redundancy data is pre-loaded into eFuse memory elements during this initial test, so that when bad addresses are detected, the system can immediately redirect access to redundant addresses without requiring complex runtime error correction algorithms. This pre-prepared redundancy mapping simplifies the overall device complexity compared to full ECC implementation.
Solution Approach 2:
The patent uses copying by creating redundant copies of memory address mappings. Instead of using complex error-correcting code algorithms, the system creates a simplified copy of the address space through eFuse-based redundancy data. When a bad word line address is detected, the system copies the necessary redundancy information from the pre-loaded eFuse data to replace the bad address, providing a straightforward address remapping mechanism that reduces device complexity.
2Reliability
If error-correcting code memory (ECC memory) is used to improve reliability, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent employs cheap short-living objects by using eFuse memory elements as disposable, simple redundancy storage. Rather than implementing expensive ECC hardware and algorithms, the system uses inexpensive eFuse elements that can be programmed once during manufacturing to store redundancy address mappings. These eFuse elements act as a low-cost alternative to complex ECC circuitry, reducing manufacturing costs while maintaining reliability through address remapping.
Solution Approach 2:
The patent applies self-service by implementing a built-in self-test function that automatically detects bad word line addresses and loads redundancy data into eFuse memory elements during the initial manufacturing process. This self-testing and self-configuring capability eliminates the need for external manual testing and configuration, reducing labor costs and simplifying the manufacturing process compared to traditional ECC memory that requires complex validation and configuration procedures.
3Reliability
If built-in self-test process is implemented to detect bad addresses, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies taking out by extracting the complexity of address remapping from the main memory operation and isolating it into a separate built-in self-test process. The self-test function independently detects bad word line addresses and loads redundancy data into eFuse elements, separating this diagnostic function from the normal memory access path. This extraction allows the main memory system to remain simple while the self-test module handles the complexity of redundancy management.
Solution Approach 2:
The patent uses an intermediary approach by introducing eFuse memory elements as an intermediate layer between the memory array and the control logic. The eFuse elements store redundancy address mappings and act as a mediator that translates bad address detections into corrected address mappings. This intermediary structure simplifies the overall system by providing a straightforward lookup mechanism rather than requiring complex real-time address transformation logic.
Data Source
AI summary
A memory device is provided, including a built-in self-test circuit and a redundancy address replacement circuit. The built-in self-test circuit coupled to a main memory cell array is configured to performing a built-in self-test process on the main memory cell array so as to provide a built-in self-test signal. The redundancy address replacement circuit includes a first redundancy circuit and a second redundancy circuit. The first redundancy circuit replaces portion of word line addresses of the main memory cell array with that of a redundancy memory block according to first redundancy data signals generated by a first test process. The second redundancy circuit, coupled to the first redundancy circuit, replaces the failure word line addresses detected in the main memory cell array with another portion of word line addresses of the redundancy memory block according to the built-in self-test signal.