Memory Redundant Cell Array Dynamic Assignment
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Solution Overview
Problem
Conventional memory architectures face challenges in managing outlayer threshold voltages, leading to failure bits due to dynamic variations and complimentary bit disturb effects, which are difficult to account for and result in erroneous logic states.
Innovation Solution
The implementation of a memory architecture that includes a redundant cell array dynamically assigned to a failed core cell array during the erasing process, using a memory controller to identify and replace failed core cell arrays with redundant ones, ensuring continuous read/write access and correcting threshold voltage issues through pre-programming, soft programming, and under-erase verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-bit memory cells are employed to conserve footprint and enhance read/write speeds, then storage density and speed are improved, but the occurrence of outlayer threshold voltages and failure bits increases due to dynamic variations and complimentary bit disturb effects
Solution Approach 1:
The patent applies preliminary action by performing pre-programming and soft programming operations on memory cells before they are fully erased. This pre-treatment stabilizes the threshold voltage distribution and reduces the occurrence of outlayer threshold voltages that lead to failure bits, thereby maintaining high reliability while preserving the speed benefits of multi-bit cells
Solution Approach 2:
The patent changes operational parameters by implementing multi-stage programming with controlled voltage levels and timing. By adjusting programming voltages, pulse widths, and verification thresholds dynamically, the system optimizes the balance between write speed and threshold voltage stability, reducing failure bits without sacrificing productivity
2Quantity of substance
If multi-bit memory cells are used to increase storage density, then footprint is reduced, but manufacturing precision requirements increase due to threshold voltage control difficulties
Solution Approach 1:
The patent segments the programming process into multiple distinct stages: pre-programming, soft programming, and final programming. Each stage uses different voltage levels and duration parameters, allowing precise control over threshold voltage distribution. This segmentation enables better manufacturing precision while maintaining high storage density through multi-bit cells
Solution Approach 2:
The patent introduces dynamic control mechanisms that adjust programming parameters based on real-time verification results. The system dynamically modifies voltage levels, pulse widths, and programming sequences to compensate for process variations, thereby achieving consistent threshold voltage control across manufacturing batches while preserving high storage density
3Device complexity
If conventional memory architectures are used, then device complexity is low, but the ability to handle outlayer threshold voltages and maintain data integrity is insufficient
Solution Approach 1:
The patent introduces intermediary control mechanisms including reference cells, verification circuits, and adaptive programming controllers. These intermediaries mediate between the simple memory array structure and the complex requirement of handling outlayer threshold voltages, maintaining data integrity without significantly increasing overall device complexity
Solution Approach 2:
The patent implements feedback loops where read verification results from each programming stage are fed back to adjust subsequent programming operations. This feedback mechanism enables the system to detect and correct threshold voltage deviations in real-time, maintaining high data integrity while using a relatively simple memory array architecture
Data Source
AI summary
A memory that employs a redundant cell array for recovery of one or more failed core cell arrays of multi-bit memory cells is described. The memory includes a plurality of core cell arrays, at least one redundant cell array, and a memory controller. The memory controller is configured to dynamically assign the redundant cell array to a failed core cell array when erasing at least a portion of the plurality of core cell arrays. The memory controller is further configured to provide read/write access to the redundant cell array when the failed core cell array is selected for read/write access.