Semiconductor Memory Redundant Latch Selective Data Fetch
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Solution Overview
Problem
In semiconductor memory devices, the inefficiency of discarding entire memory cells due to a single defect leads to low yield, and unnecessary power consumption occurs from transmitting redundant data during read operations, which is not effectively managed.
Innovation Solution
A semiconductor memory device design that includes normal and redundant memory blocks, buffer blocks, and latch blocks, with a control circuit to selectively use redundant data only when necessary, allowing for efficient data retrieval and reduced power consumption by using redundant latches and control signals to manage defective cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If redundant memory cells are provided to replace defective cells, then manufacturing yield is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory device into normal memory blocks and redundant memory blocks, with separate buffer blocks and latch blocks for each. This segmentation allows defective cells in normal blocks to be replaced by corresponding redundant cells without requiring complete redesign of the entire memory structure, thereby improving yield while managing complexity through modular organization.
Solution Approach 2:
The patent uses control signals (normal control signal and redundant control signal) to dynamically change the operational state of latch blocks. By changing the control parameter, the system can selectively activate either normal or redundant data paths, enabling yield improvement through defect replacement without permanently increasing the active complexity of the device.
2Reliability
If redundant data is transmitted during read operations, then data retrieval reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic control of the redundant latch block through control signals that are activated only when defective cells are detected. The redundant latch block selectively fetches data from the redundant buffer block based on the redundant control signal, allowing the system to adapt its data path configuration in real-time, ensuring reliable data retrieval only when necessary and thereby reducing unnecessary power consumption.
Solution Approach 2:
The patent extracts the redundant data transmission function into a separate, selectively controllable pathway. By using a dedicated redundant latch block and redundant control signal, the system can isolate and activate the redundant data path only when needed, preventing unnecessary power consumption from continuous redundant data transmission while maintaining reliability when defects are present.
3Productivity
If normal column line is replaced with redundant column line, then manufacturing yield is improved, but device complexity increases
Solution Approach 1:
The patent segments the column line structure into normal column lines and redundant column lines, with corresponding normal and redundant latch blocks. This segmentation enables targeted replacement of defective column lines with redundant ones through selective activation, improving yield while maintaining manageable complexity through clear functional separation.
Solution Approach 2:
The redundant column line and redundant latch block are designed to serve as universal replacements for any defective normal column line. The redundant latch block can fetch data from the redundant buffer block to replace data from any defective normal latch block, providing a multi-functional replacement mechanism that improves yield without requiring unique replacement structures for each defective cell.
Data Source
AI summary
A semiconductor memory device includes a normal memory block including a plurality of normal memory cells, a redundant memory block including a plurality of redundant memory cells used to replace defective cells among the normal memory cells, a normal buffer block configured to sense and amplify data stored in the normal memory block, a redundant buffer block configured to sense and amplify data stored in the redundant memory block, a normal latch block configured to fetch data from the normal buffer block and store the data based on a normal control signal, and a redundant latch block configured to selectively fetch data from the redundant buffer block and store the data based on a redundant control signal.