Memory Device Redundant Row Access Parallelization
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Solution Overview
Problem
Memory devices with redundant rows experience increased access time due to the need for address comparison before accessing memory cells, which hinders performance and clock frequency.
Innovation Solution
Implementing a memory device with multiple memory regions and data path access units, where redundant rows from one region can replace faulty rows in another region, allowing simultaneous lookup and comparison operations to reduce read access time, and pipelining write operations to manage timing constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant rows are provided in memory devices to increase yield, then reliability is improved, but memory access time increases due to address comparison requirements
Solution Approach 1:
The memory device is divided into multiple memory regions (first memory region and second memory region) with separate data path access units. Each region can be independently accessed, allowing parallel operations. The redundant rows are distributed across regions rather than centralized, enabling selective access without full array scanning.
Solution Approach 2:
The system performs preliminary actions by pre-positioning redundant rows in specific memory regions and pre-configuring the mapping between faulty rows and redundant rows. This allows the control logic to directly access the correct redundant row without performing extensive address comparison during normal operation.
2Reliability
If address comparison is performed before access to determine faulty rows, then reliability is maintained, but access time increases
Solution Approach 1:
The control logic performs the address comparison operation in advance or concurrently with the access operation. By preparing the comparison result before the actual memory access, or performing the comparison during the access cycle rather than before it, the system eliminates the sequential time penalty and maintains both reliability and speed.
Solution Approach 2:
The address comparison operation is merged with the memory access operation, allowing both to occur simultaneously or in overlapping time periods. The control logic is configured to execute comparison and access in a combined operation sequence, eliminating the need for separate sequential steps and reducing total access time.
3Reliability
If multiple redundant rows are provided across memory regions, then reliability is improved, but device complexity increases
Solution Approach 1:
The memory device is segmented into multiple regions with dedicated data path access units, allowing redundant rows to be distributed across regions. This segmentation isolates the complexity of redundancy management to individual regions rather than requiring system-wide coordination, making the overall system more manageable despite having multiple redundant rows.
Data Source
AI summary
The present invention provides a memory device comprising a memory array having a plurality of memory regions, and a plurality of data path access units, each data path access unit being associated with at least one memory region. Each memory region has at least one associated memory region selected such that the data path access unit used for that memory region is different to the data path access unit used for the at least one associated memory region. For each memory region, any redundant row used in place of a faulty row in that memory region is provided in the at least one associated memory region, and a storage is provided for maintaining a record identifying each faulty row and the redundant row to be used in place of that faulty row. On receipt of a read access request specifying a read address, a lookup operation is performed in both the memory region identified by that read address and the at least one associated memory region. Further, a comparison operation is performed to determine with reference to the storage whether the read address corresponds to one of the faulty rows as identified in the record. If the comparison operation determines that the read address does not correspond to one of the faulty rows, then the read data obtained from the memory region identified by the read address is output, whereas otherwise the read data obtained from the identified redundant row in the associated memory region is output.