Nonvolatile Memory Reference Cell Bank Segmentation

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Solution Overview

Problem

Nonvolatile memory devices experience spurious programming during read operations, leading to increased reading errors due to the higher frequency of accessing reference cells, which causes faster drift in threshold voltages and potential overlap with array cell intervals, especially in multilevel memories.

Innovation Solution

A nonvolatile memory device with an array of memory cells organized in rows and columns, featuring a dedicated reference bank and addressing circuitry that alternates the use of multiple sets of reference cells to reduce the frequency of accessing individual reference cells, using separate wordlines for different types of reference cells to mitigate the effects of spurious programming.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If reference cells are systematically accessed at every memory operation, then read and verify operations can be performed, but spurious programming occurs causing threshold voltage drift and reading errors

Engineering Contradiction:
Improvereading accuracyVSAvoidspurious programming
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The reference cell bank is divided into multiple sets (first set, second set, etc.), each containing reference cells for different threshold voltage levels. By segmenting the reference cells into multiple groups that can be alternately selected, the patent reduces the access frequency to individual reference cells while maintaining the necessary reference functions for read and verify operations.

Inventive Principle:
Principle #1Segmentation

2Productivity

If reference cells are accessed frequently for read and verify operations, then operational functionality is maintained, but threshold voltage ranges compress and overlap with array cell intervals

Engineering Contradiction:
Improveoperation speedVSAvoidthreshold voltage range separation
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent implements periodic alternation between multiple sets of reference cells during read and verify operations. Instead of continuously accessing the same reference cells, the system periodically switches between different sets, allowing each reference cell to rest and recover from the stress of frequent access, thereby preventing threshold voltage compression and maintaining proper separation between voltage ranges.

Inventive Principle:
Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution significantly reduces the adverse effects of spurious programming by evenly distributing the access load across multiple sets of reference cells, thereby minimizing reading errors and maintaining distinct threshold voltage ranges, especially in multilevel memories.

Implementation Method 1

a tunnel-oxide layer 7; During read or verify operations, an electric field E is set up between the floating-gate region 6 and the substrate 4 (in particular, the channel region 5). However, a mechanism altogether similar to that of programming causes a fraction of the electrons traveling in the channel region 5 to be deviated and trapped in the floating-gate region 6

Methodology Applied
Scientific EffectTunneling:

Data Source

PatentUS7646644B2Nonvolatile memory device with multiple references and corresponding control method
Publication Date: 2010.01.12 MICRON TECHNOLOGY INC
  • US7646644B2 patent drawing
  • US7646644B2 patent drawing
  • US7646644B2 patent drawing

AI summary

A memory device includes a group of memory cells organized in rows and columns and a first addressing circuit for addressing said memory cells of said group on the basis of a cell address. The device further includes a plurality of sets of reference cells, associated to the group, each of said set having a plurality of reference cells, and a second addressing circuit for addressing one of the reference cells during operations of read and verify of addressed memory cells.