Memory Array Reference Cell Repair for Stable Read Margins
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Solution Overview
Problem
Resistive-type memory devices face issues with defective data and reference cells, varying read margins, and interference during read operations, necessitating reliable testing and repair processes to ensure accurate data reading.
Innovation Solution
A method involving row and column repair, sense amplifier trimming, and local reference current adjustment to identify and replace defective cells, optimize current distributions, and fine-tune reference currents for improved read accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reference cells are used to provide reference current for read operations, then read operation can be implemented by comparing data current and reference current, but defective reference cells may cause reading inaccuracies
Solution Approach 1:
The patent applies preliminary action by performing row repair operations before column repair operations. During row repair, defective reference cells are identified and replaced with redundant reference cells in advance, ensuring that the reference current source is reliable before proceeding to data cell testing. This preliminary replacement prevents defective reference cells from causing reading inaccuracies in subsequent operations.
Solution Approach 2:
The patent employs parameter changes by adjusting the resistance states of reference cells through programming. By changing the resistance state parameter of reference cells (from high resistance to low resistance or vice versa), the system can selectively activate or deactivate reference cells based on their operational status, thereby excluding defective cells from providing reference current.
2Adaptability or versatility
If read margin varies for data cells at different rows and columns, then manufacturing variations are accommodated, but consistent read accuracy across all cells becomes difficult to achieve
Solution Approach 1:
The patent applies local quality by implementing column-specific repair operations after row repair. Each column can be independently tested and repaired, allowing local adjustments to reference cells and data cells in specific columns. This localized approach enables tailoring the reference current and cell characteristics to compensate for row and column-specific variations, achieving consistent read accuracy across the entire memory array despite manufacturing variations.
Solution Approach 2:
The patent employs feedback mechanisms through iterative testing and repair processes. After initial row repair, column repair operations test the actual read margins and identify cells that still exhibit reading inaccuracies. The system then applies additional repair operations based on this feedback, continuously improving read accuracy consistency until all cells meet the required performance specifications.
3Reliability
If multiple repair operations (row repair and column repair) are performed to eliminate defective cells, then reading inaccuracies are reduced, but testing and repair process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the repair process into distinct sequential stages: row repair operations followed by column repair operations. This segmentation allows each repair stage to focus on specific types of defects (row-level reference cell defects first, then column-level data cell defects), making the complex repair process more manageable and systematic while comprehensively addressing different failure modes.
Solution Approach 2:
The patent employs preliminary action by performing row repair operations before column repair operations. The row repair phase preliminarily establishes a reliable reference current source by replacing defective reference cells, creating a foundation for subsequent column repair operations to focus specifically on data cell defects. This preliminary preparation simplifies the overall process by pre-eliminating one category of defects before addressing another.
Data Source
AI summary
A method for testing and repairing a memory device is provided. The memory device includes a memory array having data cells and reference cells arranged along cell rows and cell columns. The data cells are configured to store data, and the reference cells are configured to generate a reference current for reading the data stored in the data cells. The method includes: performing a row repair, to test the reference cells in each cell row, and to replace the cell row containing at least one defective reference cell by a redundant cell row comprising additional data cells and additional reference cells; and performing a local reference current trimming, to modify a ratio of an amount of the reference cells programmed with a low resistance state over an amount of the reference cells programmed with a high resistance state for at least one of the cell rows.