Memory Reference Voltage Generator With Dual Resistor Chains
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Solution Overview
Problem
Existing voltage generators for memory devices face challenges in reducing circuit area, power consumption, and noise properties, particularly in generating stable reference voltages required for operations like programming, reading, and erasing.
Innovation Solution
The proposed solution involves a voltage generator design with a band-gap reference circuit, low-dropout regulator, and a reference voltage generator using resistor chains and decoders, where a first resistor chain receives current in both standby and active modes, and a second resistor chain receives current only in the active mode, with decoders connected to both chains to output reference voltages, reducing noise and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a voltage generator uses a single resistor chain to generate reference voltages in both standby and active modes, then the circuit area is reduced, but the noise properties deteriorate due to current fluctuations during mode switching
Solution Approach 1:
The voltage generator is divided into two separate resistor chains: a first resistor chain for standby mode operation and a second resistor chain for active mode operation. This segmentation allows each chain to be optimized for its specific operating mode, preventing noise from mode switching while maintaining compact design. The decoders are shared between both chains, reducing overall circuit area.
2Speed
If the voltage generator operates in standby mode with high current to maintain readiness, then the response speed improves, but the power consumption increases
Solution Approach 1:
The voltage generator dynamically switches between two operational configurations: in standby mode, only the first resistor chain is activated with optimized current for low power consumption while maintaining readiness; in active mode, the second resistor chain is activated to provide high current for fast response. This dynamic switching allows the system to optimize between power consumption and response speed based on operational requirements.
3Object-affected harmful factors
If the voltage generator uses separate resistor chains for standby and active modes, then the noise properties improve, but the device complexity increases
Solution Approach 1:
While using separate resistor chains for standby and active modes to reduce noise, the patent merges the decoder circuits so that the same set of decoders serves both resistor chains. This combining of shared components reduces the overall device complexity despite having multiple resistor chains, as the decoders are a common resource rather than duplicated for each chain.
4Stability of the object's composition
If the voltage generator increases current in the second resistor chain during active mode, then the reference voltage stability improves, but the power consumption increases
Solution Approach 1:
The voltage generator employs periodic mode switching between standby and active states. During standby mode, the first resistor chain operates with lower current to conserve power. When active mode is needed, the system transitions to the second resistor chain with higher current to ensure reference voltage stability during operations. This periodic activation pattern allows the system to achieve stability when needed while minimizing overall power consumption through idle periods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces circuit area, power consumption, and noise interference while ensuring stable reference voltage output, enhancing the operating performance of memory devices.
Implementation Method 1
a band-gap reference circuit configured to generate a bias voltage
Implementation Method 2
a first resistor chain including first resistors connected in series between a first power node and a second power node, a second resistor chain including second resistors connected in series between the first power node and the second power node
Data Source
AI summary
A memory device including a memory cell area having a plurality of memory cells, and a peripheral circuit area including peripheral circuits configured to control the memory cells, the peripheral circuits connected to the memory cells by at least a portion of bit lines, word lines, and select lines may be provided. The peripheral circuits may include a reference voltage generator configured to output at least one reference voltage in response to control data of a control logic. The reference voltage generator may include a first resistor chain including first resistors connected in series between a first power node and a second power node, a second resistor chain including second resistors connected in series between the first power node and the second power node, and a plurality of decoders connected to the first resistor chain and the second resistor chain.