Memory Reference Voltage Configuration for Signal Error Reduction
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Solution Overview
Problem
Existing memory systems face challenges in managing signal variations due to integrated circuit fabrication process variations, leading to reduced signaling performance and increased susceptibility to I/O signal errors, particularly in double-data-rate and phase change memory technologies.
Innovation Solution
Implementing high granularity control for reference voltage levels at the individual I/O circuit level of memory devices, allowing for different reference voltages to be configured for each signal line of a data bus to accurately distinguish logic states, thereby improving signal processing and reducing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If alternative termination schemes (VDDQ or VSSQ) are used to reduce power requirements, then power efficiency is improved, but susceptibility to I/O signal errors increases due to fabrication process variations
Solution Approach 1:
The patent applies local quality by configuring different reference voltage levels for different signal lines based on their individual voltage swing characteristics. Each signal line receives a customized reference voltage that optimizes its signal detection threshold, thereby improving reliability without sacrificing the power efficiency benefits of alternative termination schemes.
Solution Approach 2:
The patent changes the reference voltage parameter for each signal line according to its measured voltage swing characteristics. By adjusting this critical parameter individually for each signal line, the system compensates for fabrication variations and improves signal detection accuracy while maintaining the low-power termination scheme.
2Device complexity
If a single reference voltage level is used for all signal lines to simplify memory management, then device complexity is reduced, but signaling performance deteriorates due to fabrication process variations
Solution Approach 1:
The patent segments the reference voltage configuration into individual signal line-specific settings. Instead of using a single reference voltage for all signal lines, each signal line is configured with its own optimized reference voltage level based on its voltage swing characteristics, thereby improving signaling performance while keeping the management approach systematic.
Solution Approach 2:
The patent introduces dynamic configurability of reference voltage levels, allowing the memory device to adapt reference voltages based on measured voltage swing characteristics. This dynamic approach enables the system to optimize signaling performance for each signal line while maintaining a relatively simple management structure through automated configuration.
3Measurement precision
If high granularity control for reference voltage levels is implemented at the individual I/O circuit level, then signal differentiation precision is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service by enabling the memory device to automatically measure voltage swing characteristics and configure appropriate reference voltage levels for each signal line without requiring complex external management. This self-configuration capability achieves high precision signal differentiation while minimizing the complexity burden on the overall system.
Solution Approach 2:
The patent employs feedback mechanisms where voltage swing characteristics are measured and used to determine optimal reference voltage levels for each signal line. This closed-loop approach ensures high precision signal differentiation by continuously optimizing reference voltages based on actual signal characteristics, while the automated feedback process manages the complexity of individual I/O circuit configuration.
Data Source
AI summary
Techniques and mechanisms for a memory device to concurrently receive and process signals each based on a different respective reference voltage level. In an embodiment, an input/output (I/O) interface of a memory device includes receiver circuits each to process a respective signal received via a corresponding signal line of a bus. In response to one or more configuration commands, a first receiver circuit is configured to process a first signal based on a first reference voltage level and a second receiver circuit is configured to process a second signal based on a second reference voltage level. In another embodiment, a memory controller sends the one or more configuration commands to such a memory device based on an evaluation of voltage swing characteristics each corresponding to a different respective signal line of a bus.