Semiconductor Memory Reference Voltage Generation Circuit
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Solution Overview
Problem
The increasing complexity and cost of testing semiconductor memory devices due to the need for high-speed and high-capacity devices, coupled with the limitations of probe card pins, make it difficult to efficiently test multiple chips simultaneously without increasing manufacturing costs.
Innovation Solution
Incorporating a reference voltage generation circuit within the semiconductor memory device that generates a reference voltage internally during testing and can be deactivated after packaging, reducing the number of input pads required and preventing unexpected influences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of probe card pins is increased to test more chips simultaneously, then testing efficiency and productivity are improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The reference voltage supply function is segmented from the external test device and relocated to an internal reference voltage generation circuit within each chip. This segmentation allows the probe card to focus only on signal transmission pins, reducing its complexity while maintaining the ability to test multiple chips simultaneously.
Solution Approach 2:
Each chip becomes self-sufficient by incorporating its own reference voltage generation circuit, eliminating the need for external reference voltage supply through the probe card. This self-service approach reduces the number of pins required on the probe card while improving testing productivity.
2Ease of manufacture
If the number of input pads is reduced to simplify device structure, then ease of manufacture is improved, but testing capability may be compromised
Solution Approach 1:
The chip performs its own reference voltage generation internally, eliminating the need for dedicated external reference voltage input pads. This reduces the total number of input pads required while maintaining full testing capability through the internal reference voltage generation circuit.
3Productivity
If more chips are manufactured per wafer to improve productivity, then manufacturing efficiency is improved, but test inspection time increases
Solution Approach 1:
By segmenting the reference voltage supply function to individual internal circuits on each chip, the probe card requires fewer pins per chip. This reduction in pin count enables faster simultaneous testing of multiple chips on a single wafer, reducing total inspection time despite increased chip density.
4Device complexity
If the reference voltage is supplied from an external test device, then device complexity is reduced, but the number of required pins increases
Solution Approach 1:
The reference voltage generation function is extracted from the external test device and embedded within the chip itself. This extraction eliminates the need for external reference voltage supply pins, reducing the total pin count on the probe card while adding a compact internal reference voltage generation circuit.
Solution Approach 2:
The chip generates its own reference voltage internally, making it independent of external reference voltage supply. This self-service capability reduces the number of pins required on the probe card while maintaining the necessary testing functionality.
Data Source
AI summary
A semiconductor memory device includes: an input pad set configured to receive an external input signal and a reference voltage; an input buffer set configured to detect and transmit the input signal to an internal circuit of the semiconductor memory device by comparing the input signal with the reference voltage; and a reference voltage generation circuit configured to generate the reference voltage to supply the reference voltage to the input pad set and the input buffer set during a test operation, the reference voltage generation circuit being deactivated after the semiconductor memory device is packaged.