Semiconductor Memory Reference Voltage Stabilization Control
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Solution Overview
Problem
Existing semiconductor memory devices experience prolonged stabilization times and increased current consumption due to the continuous activated state of reference voltage generation circuits after the power-up period, which hampers efficient operation.
Innovation Solution
A semiconductor memory device that includes a reference voltage generation block and a control signal generation block, where the selection enable signal is activated earlier than the voltage division enable signal during a first operation period, and deactivated later than the voltage division enable signal during a second operation period, allowing for controlled on/off timings of the reference voltage generation block to optimize the stabilization time of the input reference voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reference voltage generation circuit continuously operates after power-up, then the reference voltage level is maintained, but current consumption increases and stabilization time is prolonged
Solution Approach 1:
The reference voltage generation circuit is controlled to operate periodically rather than continuously. The control signal generation block generates enable signals that activate the reference voltage generation block only during specific operation periods (first operation period for voltage division, second operation period for selection), allowing it to enter a low-power state during other times while maintaining voltage stability when needed.
2Reliability
If the reference voltage generation circuit continuously operates after power-up, then the reference voltage level is maintained, but stabilization time is prolonged
Solution Approach 1:
The control signal generation block generates enable signals in advance to activate the reference voltage generation block before it is actually needed. The first operation period enables voltage division ahead of time, and the second operation period enables selection ahead of time, allowing the reference voltage to stabilize before required operations occur, thereby reducing overall stabilization time.
3Loss of time
If the selection enable signal is activated earlier than the voltage division enable signal, then the reference voltage stabilization time is shortened, but the circuit operation complexity increases
Solution Approach 1:
The control signal generation block uses feedback from operation mode signals and internal state information to dynamically adjust the timing of enable signals. By monitoring the operational state and using this information to control the sequencing of voltage division and selection operations, the system optimizes stabilization time while managing complexity through intelligent signal coordination rather than hardwired timing.
Data Source
AI summary
A semiconductor memory device includes a reference voltage generation block suitable for selecting and outputting one of a plurality of reference voltages in response to a voltage division enable signal, as an input reference voltage, in response to a selection enable signal; and a control signal generation block suitable for generating the voltage division enable signal and the selection enable signal in response to a reference voltage information.