Memory Refresh Address Ordering for Row Hammer Protection
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Solution Overview
Problem
Volatile memory devices face data loss due to leakage current and the row hammering phenomenon, where frequent activation of specific word lines leads to data distortion in adjacent rows, necessitating inefficient target refresh operations.
Innovation Solution
A semiconductor memory device employs a reference signal generator to randomly determine enable periods and lengths, storing addresses based on access frequency and time, using order controllers to select addresses for target refresh operations, incorporating a refresh operation logic to apply mixed addresses efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional target refresh operations are performed on frequently accessed word lines, then data loss from row hammering is prevented, but refresh operation efficiency decreases due to inadequate selection of addresses requiring refresh
Solution Approach 1:
The patent applies preliminary action by performing refresh operations on word lines before data loss occurs due to row hammering. The refresh control circuit identifies frequently accessed word lines and proactively refreshes them based on access count thresholds, preventing data corruption before it happens. This is evident in the background section which states that target refresh operations are performed on word lines that are activated more than a predetermined number of times to prevent row hammering effects.
Solution Approach 2:
The patent implements dynamics by making the refresh operation adaptive to changing access patterns. The refresh control circuit dynamically adjusts which word lines receive refresh operations based on real-time access counting. When a word line's access count exceeds the threshold, it is added to the refresh target list; when it falls below, it is removed. This dynamic adjustment optimizes refresh efficiency while maintaining data reliability.
2Reliability
If refresh operations are performed on all word lines, then data loss is minimized, but power consumption and operation time increase
Solution Approach 1:
The patent applies local quality by performing refresh operations selectively on specific word lines that are prone to row hammering effects, rather than uniformly refreshing all word lines. The refresh control circuit identifies and targets only those word lines whose access counts exceed the predetermined threshold, concentrating refresh resources where they are most needed. This localized approach reduces overall power consumption while maintaining data retention reliability.
Solution Approach 2:
The patent implements partial action by performing refresh operations on only a subset of word lines - specifically those that are frequently accessed and at risk of row hammering. Instead of applying refresh to all word lines (excessive action), the system applies refresh partially to only the necessary word lines based on access pattern analysis, thereby reducing power consumption while still preventing data loss in critical areas.
3Reliability
If access count threshold is set low, then more addresses are selected for target refresh, but refresh operation overhead increases
Solution Approach 1:
The patent applies parameter changes by using a predetermined access count threshold as a configurable parameter to control the number of word lines selected for refresh. By adjusting this threshold parameter, the system can balance between data retention reliability and refresh operation time. A higher threshold reduces the number of refresh operations and their overhead, while a lower threshold increases reliability for frequently accessed lines. This parameter-based control allows optimization based on specific application requirements.
Data Source
AI summary
A semiconductor memory device, comprising: first storage logic configured to store, as the first addresses, ‘K’ addresses having different values among input addresses applied during the enable period of a reference signal, second storage logic configured to store, as second addresses, ‘L’ addresses corresponding to a time point at which the enable period of the reference signal is ended among the input addresses, an order controller configured to determine a first output order of each of the first addresses based on a number of times each of the first addresses is repeatedly input, and to determine a second output order for outputting mixed addresses obtained by mixing the first addresses based on the first output order and the second addresses together, and refresh operation logic configured to apply the mixed addresses according to the second output order, to a target refresh operation.