Memory Refresh With Address Rotation To Balance Write Times
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Solution Overview
Problem
Digital information stored in semiconductor memory devices is prone to corruption due to environmental and internal factors, leading to data loss and system failures, particularly from events like particle strikes, disturb errors, radiation, and thermal effects, which existing memory refresh methods do not adequately address.
Innovation Solution
The implementation of an optimized memory refresh operation that includes both refresh operations with and without address rotation, where data is read, checked for errors, and rewritten, with address rotation averaging write times and optimizing resource utilization to minimize re-writes and correct errors effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory refresh methods are used, then data retention is maintained, but data accuracy is insufficient due to particle strikes, disturb errors, radiation, and thermal effects
Solution Approach 1:
The patent implements preliminary error detection and correction actions by periodically refreshing memory cells and checking for errors before data corruption occurs. The refresh operation reads data from memory cells, checks for errors caused by particle strikes, disturb errors, radiation, or thermal effects, and rewrites corrected data back to the cells, preventing data accuracy degradation
2Reliability
If frequent refresh operations are performed to maintain data accuracy, then data corruption is reduced, but resource utilization increases and re-write operations multiply
Solution Approach 1:
The patent dynamically adjusts the refresh operation strategy by implementing address rotation to vary the sequence of memory cell access. This dynamic approach distributes refresh operations across different cells over time, reducing the concentration of re-write operations on the same cells and optimizing resource utilization while maintaining data accuracy
Solution Approach 2:
The patent employs periodic refresh operations that systematically cycle through memory cells in a structured sequence. By using address rotation, the periodic action is enhanced to distribute operations across different cells, reducing redundant re-writes and improving overall resource efficiency while maintaining continuous data protection
3Loss of time
If address rotation is implemented in refresh operations, then write time distribution is improved, but device complexity increases
Solution Approach 1:
The patent implements address rotation that dynamically changes the refresh sequence based on the current state of memory cell access. This dynamic address rotation distributes write operations more evenly across the memory array, reducing peak write times and improving time distribution without requiring complex external control systems
Solution Approach 2:
The address rotation mechanism operates autonomously within the memory device itself, using internal control logic to manage the refresh sequence. The device self-manages the complexity of coordinate tracking and address generation, eliminating the need for external complex control systems while achieving improved write time distribution
Data Source
AI summary
Performing refresh operation in a memory device is provided. A refresh operation without address rotation is performed in a cell array of the memory device. Performing the refresh operation without address rotation is repeated for a predetermined number of times. After repeating performing the refresh operation with address rotation for the predetermined number of times, a refresh operation with address rotation is performed in the cell array.