Memory Refresh Rate Based Throttling for SoC Bandwidth Control
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Solution Overview
Problem
Real-time processors face timing violations due to high utilization of shared memory by other processors, which causes increased power and thermal dissipation, leading to insufficient mitigation by reducing clock frequencies, especially when best effort processors continue to generate significant traffic.
Innovation Solution
Implementing a system on chip (SoC) that controls the bandwidth of processors based on the refresh rate of memory, using a quality of service manager to send instructions to reduce or restore bandwidth in response to high or low memory refresh rate thresholds, thereby managing memory utilization more accurately than ambient temperature-based methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If clock frequencies of processors are reduced to mitigate memory utilization, then power dissipation decreases, but memory access speed deteriorates and time sensitive requirements are still violated
Solution Approach 1:
The patent changes the control parameter from clock frequency to memory bandwidth utilization. Instead of reducing processor clock frequencies, the system monitors memory bandwidth usage and dynamically adjusts processor access to shared memory based on refresh rate thresholds, thereby controlling power dissipation without compromising processor execution speed
Solution Approach 2:
The patent implements a feedback mechanism where the memory controller monitors the refresh rate of DRAM cells and sends notifications to the quality of service manager. This feedback loop enables dynamic adjustment of processor bandwidth allocation based on actual memory thermal conditions, allowing the system to respond to changing power dissipation requirements while maintaining optimal performance
2Temperature
If clock frequencies are reduced to reduce memory traffic, then thermal dissipation decreases, but best effort processors continue to generate significant traffic causing timing violations
Solution Approach 1:
The patent introduces dynamic bandwidth allocation that adjusts processor access rights in real-time based on memory thermal conditions. When the memory controller detects high refresh rates indicating excessive thermal dissipation, it notifies the quality of service manager to reduce bandwidth for best effort processors, thereby dynamically controlling thermal dissipation while ensuring real-time processors maintain full access
Solution Approach 2:
The patent segments processor access to shared memory by implementing quality of service classes that differentiate between real-time processors and best effort processors. This segmentation allows selective bandwidth control where best effort processors can be throttled during high thermal conditions while real-time processors maintain guaranteed access, solving the problem of inconsistent timing compliance
3Stability of the object's composition
If DRAM refresh rate is increased to retain content at high temperature, then data retention improves, but memory access speed decreases increasing likelihood of timing violations
Solution Approach 1:
The patent performs preliminary monitoring of DRAM refresh rates to detect conditions of high thermal dissipation before they cause timing violations. By continuously monitoring the refresh rate and comparing it against thresholds, the system can proactively adjust processor bandwidth allocation before memory access speed degradation impacts real-time processing requirements
Data Source
AI summary
Various embodiments include methods for controlling memory utilization to accommodate changes in memory accessibility due to memory refreshes include controlling bandwidth of at least one processor based on a refresh rate of a memory. Some embodiments may include receiving the refresh rate of the memory at a memory controller, and determining whether the refresh rate of the memory violates a high or low memory refresh rate threshold, sending an instruction configured to reduce or restore the bandwidth of the at least one processor in response to the determination. In some embodiments the methods may be performed by a quality of service manager, which may be part of a memory controller.