Memory Controller Refresh Scheduling for Multi-Bank DRAM Latency
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Solution Overview
Problem
Existing memory architectures face challenges in efficiently managing refresh commands for large DRAM chips, leading to increased latency and reduced efficiency due to the need for all banks to be refreshed within a specific time interval, which disrupts read and write operations.
Innovation Solution
A memory controller that intelligently schedules medium-granularity refresh commands, such as the 2-bank refresh (REF2b) command, by selecting the order of refresh based on lowest-cost estimates of memory banks in the command queue, considering factors like command count, quality-of-service indicators, page state, and access type to minimize latency and maximize efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If all banks are refreshed simultaneously using traditional refresh commands, then the refresh operation is simple to implement, but the command latency increases significantly and read/write operations are disrupted
Solution Approach 1:
The patent divides the memory bank refresh operation into segments by introducing medium-granularity refresh commands that can refresh multiple banks simultaneously rather than refreshing all banks sequentially. This segmentation allows parallel refresh operations across different banks, reducing the total refresh time and command latency while maintaining implementation simplicity through a unified command structure.
2Reliability
If all banks are refreshed within the required time interval, then data reliability is maintained, but memory bus utilization decreases and ongoing read/write operations are blocked
Solution Approach 1:
The patent implements preliminary action by allowing refresh operations to be scheduled and executed in advance during periods of low memory bus activity. The medium-granularity refresh commands can be issued before critical read/write operations occur, ensuring data reliability is maintained without blocking ongoing memory transactions. The system proactively manages refresh timing to minimize disruption to productive memory operations.
3Quantity of substance
If larger DRAM chip sizes are used to increase storage capacity, then storage capacity improves, but the refresh time increases and pending read/write command latency increases
Solution Approach 1:
The patent merges multiple bank refresh operations into a single medium-granularity refresh command that can execute concurrently across multiple banks. This combining approach allows the system to refresh larger memory capacities more efficiently by performing multiple refresh operations simultaneously rather than sequentially, thereby reducing the overall refresh time and its impact on pending read/write commands.
4Loss of time
If medium-granularity refresh commands are used to reduce latency, then command latency decreases, but the complexity of scheduling and managing refresh operations increases
Solution Approach 1:
The patent applies universality by designing a unified medium-granularity refresh command structure that can handle multiple banks simultaneously while maintaining a consistent command interface. This universal command format simplifies the scheduling logic compared to managing multiple different refresh command types, as the same command structure can be applied across different memory configurations and bank counts, reducing overall scheduling complexity.
Data Source
AI summary
A data processor includes a memory accessing agent for generating memory access requests for a memory that includes a plurality of banks, and a memory controller. The memory controller includes a command queue and a refresh controller. The command queue is for storing the memory access requests. The refresh controller is coupled to the command queue and is operable to select an order of providing multi-bank refresh commands to sets of selected banks of the plurality of banks in the memory in response to lowest-cost estimates of the banks of the memory based on the memory access requests in the command queue.