Memory Device Refresh Control for Mixed Capacity Systems

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Solution Overview

Problem

Volatile semiconductor memory devices face inefficiencies in refresh operations due to varying storage capacities among connected memory devices, leading to suboptimal performance and data retention.

Innovation Solution

Implementing a method where memory devices with different storage capacities receive distinct setting signals, allowing them to perform different numbers of refresh operations during the same duration, ensuring efficient refresh operations based on their specific storage capacities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory devices with different storage capacities perform the same number of refresh operations during the same refresh period, then the refresh operation is simple to control, but the refresh efficiency is reduced for devices with smaller storage capacities

Engineering Contradiction:
Improverefresh efficiencyVSAvoidrefresh control complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies local quality by configuring each memory device with device-specific refresh parameters (number of refresh operations and refresh period duration) that match its storage capacity. Smaller capacity devices perform fewer refresh operations over a longer period, while larger capacity devices perform more refresh operations over a shorter period, optimizing refresh efficiency for each device's characteristics.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements dynamics by making refresh parameters adjustable and device-specific rather than fixed and uniform. The memory controller dynamically configures different numbers of refresh operations and different refresh period durations based on each memory device's storage capacity, allowing the refresh system to adapt to varying device characteristics.

Inventive Principle:
Principle #15Dynamics

2Productivity

If memory devices with different storage capacities perform different numbers of refresh operations during the same refresh period, then the refresh efficiency is improved, but the control complexity increases

Engineering Contradiction:
Improverefresh efficiencyVSAvoidrefresh control complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies self-service by embedding device-specific refresh parameters directly within each memory device's configuration. Each memory device autonomously performs the appropriate number of refresh operations based on its pre-configured parameters, reducing the control burden on the memory controller while maintaining optimized refresh efficiency for each device's storage capacity.

Inventive Principle:
Principle #25Self-service

3Productivity

If memory devices with different storage capacities have the same refresh period duration, then the timing is simple to synchronize, but the refresh efficiency is reduced for devices with smaller storage capacities

Engineering Contradiction:
Improverefresh efficiencyVSAvoidrefresh timing synchronization
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The patent applies local quality by assigning different refresh period durations to memory devices based on their storage capacities. Devices with smaller storage capacities operate over longer refresh periods with fewer operations, while devices with larger storage capacities use shorter refresh periods with more operations, allowing each device to be optimized independently while maintaining system-wide synchronization through the controller.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10325643B2Method of refreshing memory device and memory system based on storage capacity
Publication Date: 2019.06.18 SAMSUNG ELECTRONICS CO LTD
  • US10325643B2 patent drawing
  • US10325643B2 patent drawing
  • US10325643B2 patent drawing

AI summary

A method of operating a memory device, a first setting signal is received by a first memory device among a plurality of memory devices. The first memory device has a first storage capacity, and the memory devices may be connected to one another by a single channel. A second setting signal is received by a second memory device among the plurality of memory devices. The second memory device has a second storage capacity different from the first storage capacity. N refresh operations are performed by the first memory device based on a first refresh command and the first setting signal during a first refresh period. M refresh operations are performed by the second memory device based on a second refresh command and the second setting signal during a second refresh period. A duration of the second refresh period is substantially the same as a duration of the first refresh period.